1. 29 Nov, 2011 6 commits
    • Timur Tabi's avatar
      powerpc/85xx: clean up and document the QE/FMAN microcode macros · f2717b47
      Timur Tabi authored
      Several macros are used to identify and locate the microcode binary image
      that U-boot needs to upload to the QE or Fman.  Both the QE and the Fman
      use the QE Firmware binary format to package their respective microcode data,
      which is why the same macros are used for both.  A given SOC will only have
      a QE or an Fman, so this is safe.
      Unfortunately, the current macro definition and usage has inconsistencies.
      For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman
      firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address
      of NAND.  There's no way to know by looking at a variable how it's supposed
      to be used.
      In the future, the code which uploads QE firmware and Fman firmware will
      be merged.
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Timur Tabi's avatar
      powerpc/85xx: always implement the work-around for Erratum SATA_A001 · fbc20aab
      Timur Tabi authored
      On the P1022/P1013, the work-around for erratum SATA_A001 was implemented
      only if U-Boot initializes SATA, but SATA is not initialized by default.  So
      move the work-around to the CPU initialization function, so that it's always
      executed on the SOCs that need it.
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Timur Tabi's avatar
      powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h · 3e0529f7
      Timur Tabi authored
      Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA
      controller, so it should be defined in config_mpc85xx.h instead of the various
      board header files.  So now CONFIG_FSL_SATA_V2 is always defined on the P1013,
      P1022, P2041, P3041, P5010, and P5020.  It was already defined for the
      P1010 and P1014.
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • York Sun's avatar
      powerpc/85xx: Add workaround for erratum A-003474 · 4108508a
      York Sun authored
      Erratum A-003474: Internal DDR calibration circuit is not supported
      Experience shows no significant benefit to device operation with
      auto-calibration enabled versus it disabled. To ensure consistent timing
      results, Freescale recommends this feature be disabled in future customer
      products. There should be no impact to parts that are already operating
      in the field.
      Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
      1. Write a value of 0x0000_0015 to the register at offset
      	CCSRBAR + DDR OFFSET + 0xf30
      2. Write a value of 0x2400_0000 to the register at offset
      	CCSRBAR + DDR OFFSET + 0xf54
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Jia Hongtao's avatar
      powerpc/85xx: fixup flexcan device tree clock-frequency · 33c87536
      Jia Hongtao authored
      Make the fixup matchable with dts and kernel.  Update the compatible from
      "fsl,flexcan-v1.0" to "fsl,p1010-flexcan" and Change the "clock-freq"
      property to "clock-frequency".  We also change flexcan frequency from
      CCB-clock to CCB-clock/2 according to P1010 spec.
      We now keep the old interfaces to make previous kernel work. They should
      be removed in the future.
      Signed-off-by: default avatarJia Hongtao <B38951@freescale.com>
      Signed-off-by: default avatarLi Yang <leoli@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Kumar Gala's avatar
      powerpc/85xx: Add workaround for erratum CPU-A003999 · 43f082bb
      Kumar Gala authored
      Erratum A-003999: Running Floating Point instructions requires special
      Floating point arithmetic operations may result in an incorrect value.
      Perform a read modify write to set bit 7 to a 1 in SPR 977 before
      executing any floating point arithmetic operation. This bit can be set
      when setting MSR[FP], and can be cleared when clearing MSR[FP].
      Alternatively, the bit can be set once at boot time, and never cleared.
      There will be no performance degradation due to setting this bit.
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
  2. 28 Nov, 2011 3 commits
  3. 27 Nov, 2011 14 commits
  4. 25 Nov, 2011 2 commits
  5. 24 Nov, 2011 2 commits
  6. 23 Nov, 2011 13 commits