1. 24 Nov, 2014 1 commit
  2. 21 Nov, 2014 1 commit
  3. 05 Jun, 2014 2 commits
  4. 16 May, 2014 1 commit
  5. 23 Apr, 2014 2 commits
    • York Sun's avatar
      powerpc/mpc85xx: Add workaround for erratum A007212 · c3678b09
      York Sun authored
      
      
      Erratum A007212 for DDR is about a runaway condition for DDR PLL
      oscilliator. Please refer to erratum document for detail.
      For this workaround to work, DDR PLL needs to be disabled in RCW.
      However, u-boot needs to know the expected PLL ratio. We put the
      ratio in a reserved field RCW[18:23]. U-boot will skip this workaround
      if DDR PLL ratio is set, or the reserved field is not set.
      
      Workaround for erratum A007212 applies to selected versions of
      B4/T4 SoCs. It is safe to apply the workaround to all versions. It
      is helpful for upgrading SoC without changing u-boot. In case DDR
      PLL is disabled by RCW (part of the erratum workaround), we need this
      u-boot workround to bring up DDR clock.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      c3678b09
    • Nikhil Badola's avatar
      fsl/usb: Workaround for USB erratum-A007075 · 11856919
      Nikhil Badola authored
      
      
      Put a delay of 5 millisecond after reset so that ULPI phy
      gets enough time to come out of reset. Erratum A007075 applies
      to following SOCs and their variants, if any
              P1010 rev 1.0
              B4860 rev 1.0, 2.0
              P4080 rev 2.0, 3.0
      Signed-off-by: default avatarNikhil Badola <nikhil.badola@freescale.com>
      Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
      11856919
  6. 07 Mar, 2014 2 commits
  7. 21 Jan, 2014 1 commit
  8. 16 Oct, 2013 1 commit
  9. 10 Sep, 2013 1 commit
    • York Sun's avatar
      powerpc/mpc85xx: Add workaround for erratum A-005125 · 954a1a47
      York Sun authored
      
      
      In a very rare condition, a system hang is possible when the e500 core
      initiates a guarded load to PCI / PCIe /SRIO performs a coherent write
      to memory. Please refer to errata document for more details. This erratum
      applies to the following SoCs and their variants, if any.
      
      BSC9132
      BSC9131
      MPC8536
      MPC8544
      MPC8548
      MPC8569
      MPC8572
      P1010
      P1020
      P1021
      P1022
      P1023
      P2020
      C29x
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      CC: Scott Wood <scottwood@freescale.com>
      954a1a47
  10. 20 Aug, 2013 2 commits
    • Shengzhou Liu's avatar
      powerpc/sec: Add workaround for SEC A-003571 · 424bf942
      Shengzhou Liu authored
      
      
      Multiple read/write transactions initiated by security
      engine may cause system to hang.
      Workaround: set MCFGR[AXIPIPE] to 0 to avoid hang.
      Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
      Acked-by: default avatarYork Sun <yorksun@freescale.com>
      424bf942
    • Chunhe Lan's avatar
      fsl_i2c: add workaround for the erratum I2C A004447 · 9c3f77eb
      Chunhe Lan authored
      
      
      This workaround is for the erratum I2C A004447. Device reference
      manual provides a scheme that allows the I2C master controller
      to generate nine SCL pulses, which enable an I2C slave device
      that held SDA low to release SDA. However, due to this erratum,
      this scheme no longer works. In addition, when I2C is used as
      a source of the PBL, the state machine is not able to recover.
      
      At the same time, delete the reduplicative definition of SVR_VER
      and SVR_REV. The SVR_REV is the low 8 bits rather than the low 16
      bits of svr. And we use the CONFIG_SYS_FSL_A004447_SVR_REV macro
      instead of hard-code value 0x10, 0x11 and 0x20.
      
      The CONFIG_SYS_FSL_A004447_SVR_REV = 0x00 represents that one
      version of platform has this I2C errata. So enable this errata
      by IS_SVR_REV(svr, maj, min) function.
      Signed-off-by: default avatarZhao Chenhui <chenhui.zhao@freescale.com>
      Signed-off-by: default avatarChunhe Lan <Chunhe.Lan@freescale.com>
      Cc: Scott Wood <scottwood@freescale.com>
      Cc: Heiko Schocher <hs@denx.de>
      9c3f77eb
  11. 09 Aug, 2013 1 commit
  12. 24 Jul, 2013 1 commit
  13. 20 Jun, 2013 1 commit
  14. 02 May, 2013 1 commit
  15. 30 Jan, 2013 1 commit
  16. 28 Nov, 2012 3 commits
    • Yuanquan Chen's avatar
      powerpc/p4080ds: fix PCI-e x8 link training down failure · c0a4e6b8
      Yuanquan Chen authored
      
      
      Due to SerDes configuration error, if we set the PCI-e controller link width
      as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
      PCI-e slot, it fails to train down to the PCI-e device's link width. According
      to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
      u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
      RC and EP.
      Signed-off-by: default avatarYuanquan Chen <B41889@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      c0a4e6b8
    • Timur Tabi's avatar
      powerpc/85xx: implement check for erratum A-004580 work-around · d607b968
      Timur Tabi authored
      
      
      The work-around for erratum A-004580 ("Internal tracking loop can falsely
      lock causing unrecoverable bit errors") is implemented via the PBI
      (pre-boot initialization code, typically attached to the RCW binary).
      This is because the work-around is easier to implement in PBI than in
      U-Boot itself.
      
      It is still useful, however, for the 'errata' command to tell us whether
      the work-around has been applied.  For A-004580, we can do this by verifying
      that the values in the specific registers that the work-around says to
      update.
      
      This change requires access to the SerDes lane sub-structure in
      serdes_corenet_t, so we make it a named struct.
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      d607b968
    • Timur Tabi's avatar
      powerpc/85xx: implement check for erratum A-004849 work-around · 0118033b
      Timur Tabi authored
      
      
      The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a
      deadlock under certain traffic patterns causing the system to hang") is
      implemented via the PBI (pre-boot initialization code, typically attached
      to the RCW binary).  This is because the work-around is easier to implement
      in PBI than in U-Boot itself.
      
      It is still useful, however, for the 'errata' command to tell us whether
      the work-around has been applied.  For A-004849, we can do this by verifying
      that the values in the specific registers that the work-around says to
      update.
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      0118033b
  17. 22 Oct, 2012 4 commits
    • York Sun's avatar
      powerpc/mpc85xx: Add workaround for DDR erratum A004934 · a1d558a2
      York Sun authored
      
      
      After DDR controller is enabled, it performs a calibration for the
      transmit data vs DQS paths. During this calibration, the DDR controller
      may make an inaccurate calculation, resulting in a non-optimal tap point.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      a1d558a2
    • York Sun's avatar
      powerpc/mpc85xx: software workaround for DDR erratum A-004468 · eb539412
      York Sun authored
      
      
      Boot space translation utilizes the pre-translation address to select
      the DDR controller target. However, the post-translation address will be
      presented to the selected DDR controller. It is possible that the pre-
      translation address selects one DDR controller but the post-translation
      address exists in a different DDR controller when using certain DDR
      controller interleaving modes. The device may fail to boot under these
      circumstances. Note that a DDR MSE error will not be detected since DDR
      controller bounds registers are programmed to be the same when configured
      for DDR controller interleaving.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      eb539412
    • Liu Gang's avatar
      powerpc/srio: Workaround for srio erratrm a004034 · d59c5570
      Liu Gang authored
      
      
      Erratum: A-004034
      Affects: SRIO
      
      Description: During port initialization, the SRIO port performs
      lane synchronization (detecting valid symbols on a lane) and
      lane alignment (coordinating multiple lanes to receive valid data
      across lanes). Internal errors in lane synchronization and lane
      alignment may cause failure to achieve link initialization at
      the configured port width.
      
      An SRIO port configured as a 4x port may see one of these scenarios:
      
      1.	One or more lanes fails to achieve lane synchronization.
      	Depending on which lanes fail, this may result in downtraining
      	from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane).
      
      2.	The link may fail to achieve lane alignment as a 4x, even
      	though all 4 lanes achieve lane synchronization, and downtrain
      	to a 1x. An SRIO port configured as a 1x port may fail to complete
      	port initialization (PnESCSR[PU] never deasserts) because of
      	scenario 1.
      
      Impact: SRIO port may downtrain to 1x, or may fail to complete
      link initialization. Once a port completes link initialization
      successfully, it will operate normally.
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      d59c5570
    • Zang Roy-R61911's avatar
      P4080/esdhc: make the P4080 ESDHC13 errata workaround conditional · 4e0be34a
      Zang Roy-R61911 authored
      
      
      P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the
      workaround conditional.
      In formal release document, the errata number should be ESDHC13 instead
      of ESDHC136.
      Signed-off-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      4e0be34a
  18. 23 Aug, 2012 2 commits
    • Scott Wood's avatar
      powerpc/fsl-corenet: work around erratum A004510 · 33eee330
      Scott Wood authored
      
      
      Erratum A004510 says that under certain load conditions, modified
      cache lines can be discarded, causing data corruption.
      
      To work around this, several CCSR and DCSR register updates need to be
      made in a careful manner, so that there is no other transaction in
      corenet when the update is made.
      
      The update is made from a locked cacheline, with a delay before to flush
      any previous activity, and a delay after to flush the CCSR/DCSR update.
      We can't use a readback because that would be another corenet
      transaction, which is not allowed.
      
      We lock the subsequent cacheline to prevent it from being fetched while
      we're executing the previous cacheline.  It is filled with nops so that a
      branch doesn't cause us to fetch another cacheline.
      
      Ordinarily we are running in a cache-inhibited mapping at this point, so
      we temporarily change that.  We make it guarded so that we should never
      see a speculative load, and we never do an explicit load.  Thus, only the
      I-cache should ever fill from this mapping, and we flush/unlock it
      afterward.  Thus we should avoid problems from any potential cache
      aliasing between inhibited and non-inhibited mappings.
      
      NOTE that if PAMU is used with this patch, it will need to use a
      dedicated LAW as described in the erratum.  This is the responsibility
      of the OS that sets up PAMU.
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      33eee330
    • York Sun's avatar
      powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditional · 57125f22
      York Sun authored
      
      
      This erratum applies to the following SoCs:
      P4080 rev 1.0, 2.0, fixed in rev 3.0
      P2041 rev 1.0, 1.1, fixed in rev 2.0
      P3041 rev 1.0, 1.1, fixed in rev 2.0.
      
      Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround
      may degrade performance. P4080 erratum CPU22 shares the same workaround.
      So it is always enabled for P4080. For other SoCs, it can be disabled by
      hwconfig with syntax:
      
      fsl_cpu_a011:disable
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      57125f22
  19. 06 Jul, 2012 3 commits
  20. 29 Nov, 2011 2 commits
    • York Sun's avatar
      powerpc/85xx: Add workaround for erratum A-003474 · 4108508a
      York Sun authored
      
      
      Erratum A-003474: Internal DDR calibration circuit is not supported
      
      Impact:
      Experience shows no significant benefit to device operation with
      auto-calibration enabled versus it disabled. To ensure consistent timing
      results, Freescale recommends this feature be disabled in future customer
      products. There should be no impact to parts that are already operating
      in the field.
      
      Workaround:
      Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
      1. Write a value of 0x0000_0015 to the register at offset
      	CCSRBAR + DDR OFFSET + 0xf30
      2. Write a value of 0x2400_0000 to the register at offset
      	CCSRBAR + DDR OFFSET + 0xf54
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      4108508a
    • Kumar Gala's avatar
      powerpc/85xx: Add workaround for erratum CPU-A003999 · 43f082bb
      Kumar Gala authored
      
      
      Erratum A-003999: Running Floating Point instructions requires special
      initialization.
      
      Impact:
      Floating point arithmetic operations may result in an incorrect value.
      
      Workaround:
      Perform a read modify write to set bit 7 to a 1 in SPR 977 before
      executing any floating point arithmetic operation. This bit can be set
      when setting MSR[FP], and can be cleared when clearing MSR[FP].
      Alternatively, the bit can be set once at boot time, and never cleared.
      There will be no performance degradation due to setting this bit.
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      43f082bb
  21. 08 Nov, 2011 1 commit
  22. 03 Oct, 2011 2 commits
  23. 30 Sep, 2011 3 commits
  24. 29 Apr, 2011 1 commit