- 09 Jan, 2014 2 commits
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Henrik Nordström authored
Provide a way to use any host file or device as a block device in U-Boot. This can be used to provide filesystem access within U-Boot to an ext2 image file on the host, for example. The support is plumbed into the filesystem and partition interfaces. We don't want to print a message in the driver every time we find a missing device. Pass the information back to the caller where a message can be printed if desired. Signed-off-by:
Henrik Nordström <henrik@henriknordstrom.net> Signed-off-by:
Simon Glass <sjg@chromium.org> - Removed change to part.c get_device_and_partition() Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Add an implementation of the CRC8 algorithm. This is required by the TPM emulation, but is probably useful to U-Boot in general. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Simon Glass <sjg@chromium.org>
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- 06 Jan, 2014 2 commits
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git://git.denx.de/u-boot-mpc85xxTom Rini authored
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git://git.denx.de/u-boot-onenandTom Rini authored
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- 02 Jan, 2014 11 commits
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Prabhakar Kushwaha authored
Define QIXIS_RST_FORCE_MEM to reset on-board DDR-DIMM before start accessing it. Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com>
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Shaohui Xie authored
The BOOT_LOC setting in rcw cfg is wrong, set it to Memory complex 1. Signed-off-by:
Shaohui Xie <Shaohui.Xie@freescale.com>
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Shaohui Xie authored
Signed-off-by:
Shaohui Xie <Shaohui.Xie@freescale.com>
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Scott Wood authored
This fixes a build break due to excessively large NAND data structures. Signed-off-by:
Scott Wood <scottwood@freescale.com> Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Shengzhou Liu authored
CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used, update it to new CONFIG_USB_MAX_CONTROLLER_COUNT. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@freescale.com>
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York Sun authored
Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to reduce the image size, by taking advantage of the new nand_ecclayout structure. Signed-off-by:
York Sun <yorksun@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Scott Wood <scottwood@freescale.com>
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York Sun authored
Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to reduce the image size, by taking advantage of the new nand_ecclayout structure. Signed-off-by:
York Sun <yorksun@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Scott Wood <scottwood@freescale.com>
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Priyanka Jain authored
Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by:
Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by:
Priyanka Jain <Priyanka.Jain@freescale.com>
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Prabhakar Kushwaha authored
Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion) is 0 i.e. 0 ns hold time on writes. This may not work on higher clock freqencies. So, Increase TCH as 0x8 i.e. 8 ip_clk. Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com>
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Prabhakar Kushwaha authored
CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary review purpose. So, use CONFIG_SPL_NAND_BOOT config. Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com>
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Prabhakar Kushwaha authored
T1040QDS has 256KB SRAM. Comment is showing wrong information. So update the comment. Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com>
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- 31 Dec, 2013 1 commit
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Marek Vasut authored
Fix unaligned access in OneNAND core. The problem is that the ffchars[] array is an array of "unsigned char", but in onenand_write_ops_nolock() can be passed to the memcpy_16() function. The memcpy_16() function will treat the buffer as an array of "unsigned short", thus triggering unaligned access if the compiler decided ffchars[] to be not aligned. I managed to trigger the problem with regular ELDK 5.4 GCC compiler. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@ti.com>
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- 20 Dec, 2013 2 commits
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Tom Rini authored
With changes to the rtl8169 ethernet to improve cache support, we have needed additional cache functions for mpc8245. As the board maintainer has been unresponsive, remove this board. Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by:
Tom Rini <trini@ti.com>
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Łukasz Majewski authored
Update boards.cfg entries for Samsung's GONI and Universal_C210 maintainers entry. Signed-off-by:
Lukasz Majewski <l.majewski@samsung.com> Acked-by:
Minkyu Kang <mk7.kang@samsung.com>
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- 19 Dec, 2013 3 commits
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git://git.denx.de/u-boot-spiTom Rini authored
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Poddar, Sourav authored
claim spi bus while doing memory copy, this will set up the spi controller device control register before doing a memory read. Signed-off-by:
Sourav Poddar <sourav.poddar@ti.com> Tested-by:
Yebio Mesfin <ymesfin@ti.com> Reviewed-by:
Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Poddar, Sourav authored
Add config to support bank address register. Signed-off-by:
Sourav Poddar <sourav.poddar@ti.com> Tested-by:
Yebio Mesfin <ymesfin@ti.com> Reviewed-by:
Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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- 18 Dec, 2013 18 commits
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git://git.denx.de/u-boot-usbTom Rini authored
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Marek Vasut authored
Fix the register access in EHCI HCD. We need to use address of the register as an ehci_writel() argument. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
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Marek Vasut authored
In case the controller is not initialized, we shall not de-initialize it. As the control structure will not be filled, we will produce a null ptr dereference if the controller is not inited. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
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Marek Vasut authored
The detection function of the EHCI PCI controller was really cryptic, add a beefy comment and clean the portion of the code up a bit. No change in the logic of the code. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
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Lukasz Majewski authored
Provide default Poll Timeout value for Trats board. Signed-off-by:
Lukasz Majewski <l.majewski@samsung.com>
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Lukasz Majewski authored
Code cleanup for dfu_bind_config function Signed-off-by:
Lukasz Majewski <l.majewski@samsung.com>
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Lukasz Majewski authored
It is necessary to deter the host from sending subsequent DFU_GETSTATUS request in the case of e.g. writing the buffer to medium. Here the timeout is increased when we fill up the whole buffer. This delay allows eMMC memory to perform its internal operations. Otherwise we end up with HOST's error regarding GET_STATUS receive timeout. Signed-off-by:
Lukasz Majewski <l.majewski@samsung.com>
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Lukasz Majewski authored
The method for exporting size of allocated buffer is provided. It is afterwards used by USB's dfu function code. Signed-off-by:
Lukasz Majewski <l.majewski@samsung.com>
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Yen Lin authored
The RDY bit indicates that a transfer is complete. This needs to be cleared by SW before every single HW transaction, rather than only at the start of each SW transaction (those being made up of n HW transactions). It seems that earlier HW may have cleared this bit autonomously when starting a new transfer, and hence this code was not needed in practice. However, this is generally a good idea in all cases. In Tegra124, the HW behaviour appears to have changed, and SW must explicitly clear this bit. Otherwise, SW will believe that transfers have completed when they have not, and may e.g. read stale data from the RX FIFO. Signed-off-by:
Yen Lin <yelin@nvidia.com> [swarren, rewrote commit description, unified duplicate RDY clearing code and moved it right before the start of the HW transaction, unconditionally exit loop after reading RX data, rather than checking if TX FIFO is empty, since it is guaranteed to be] Signed-off-by:
Stephen Warren <swarren@nvidia.com> Reviewed-by:
Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Nobuhiro Iwamatsu authored
This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by:
Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by:
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by:
Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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Luka Perkov authored
Add support for Macronix MX25L2006E SPI flash. Signed-off-by:
Luka Perkov <luka@openwrt.org> Reviewed-by:
Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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Luka Perkov authored
All other hex values in sf_probe.c are in lower case so we should fix this one too. Signed-off-by:
Luka Perkov <luka@openwrt.org> Reviewed-by:
Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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Masahiro Yamada authored
Before this commit, a broken pipe error sometimes happened when building lcd4_lwmon5 board with Buildman. This commit re-writes build rules of u-boot.spr and u-boot-img-spl-at-end.bin more simply without using a pipe. Besides fixing a broken pipe error, this commit gives us other advantages: - Do not generate intermidiate files, spl/u-boot-spl.img and spl/u-boot-spl-pad.img for creating u-boot.spr - Do not generate an intermidiate file, u-boot-pad.img for creating u-boot-img-spl-at-end.bin Such intermidiate files were not deleted by "make clean" or "make mrpropr". Nor u-boot-pad.img was ignored by git. Signed-off-by:
Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by:
Stefan Roese <sr@denx.de>
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Bo Shen authored
Fix the typo error for mrproper from mkproper. Signed-off-by:
Bo Shen <voice.shen@atmel.com> Acked-by:
Simon Glass <sjg@chromium.org>
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Yoshihiro Shimoda authored
Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Yoshihiro Shimoda authored
SH7753 has two fast ethernet controllers and two gigabit ethernet controllers. It is similar to SH7757. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Yoshihiro Shimoda authored
The SH7753 EVB board has SH7753, 512MB DDR3-SDRAM, SPI ROM, Gigabit Ethernet, and eMMC. This patch support the following functions: - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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- 17 Dec, 2013 1 commit
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Nikita Kiryanov authored
If we change to software ecc and then back to hardware ecc, the nand ecc ops pointers are populated with incorrect function pointers. This is related to the way nand_scan_tail() handles assigning functions to ecc ops: If we are switching to software ecc/no ecc, it assigns default functions to the ecc ops pointers unconditionally, but if we are switching to hardware ecc, the default hardware ecc functions are assigned to ops pointers only if these pointers are NULL (so that drivers could set their own functions). In the case of omap_gpmc.c driver, when we switch to sw ecc, sw ecc functions are assigned to ecc ops by nand_scan_tail(), and when we later switch to hw ecc, the ecc ops pointers are not NULL, so nand_scan_tail() does not overwrite them with hw ecc functions. The result: sw ecc functions used to write hw ecc data. Clear the ecc ops pointers in omap_gpmc.c when switching ecc types, so that ops which were not assigned by the driver will get the correct default values from nand_scan_tail(). Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by:
Nikita Kiryanov <nikita@compulab.co.il>
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