1. 30 Apr, 2012 11 commits
    • Andy Fleming's avatar
      Allow for parallel builds and saved output · f588bb03
      Andy Fleming authored
      
      
      The MAKEALL script cleverly runs make with the appropriate options
      to use all of the cores on the system, but your average U-Boot build
      can't make much use of more than a few cores.  If you happen to have
      a many-core server, your builds will leave most of the system idle.
      
      In order to make full use of such a system, we need to build multiple
      targets in parallel, and this requires directing make output into
      multiple directories. We add a BUILD_NBUILDS variable, which allows
      users to specify how many builds to run in parallel.
      When BUILD_NBUILDS is set greater than 1, we redefine BUILD_DIR for
      each build to be ${BUILD_DIR}/${target}. Also, we make "./build" the
      default BUILD_DIR when BUILD_NBUILDS is greater than 1.
      
      MAKEALL now tracks which builds are still running, and when one
      finishes, it starts a new build.
      
      Once each build finishes, we run "make tidy" on its directory, to reduce
      the footprint.
      
      As a result, we are left with a build directory with all of the built
      targets still there for use, which means anyone who wanted to use
      MAKEALL as part of a test harness can now do so.
      
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      f588bb03
    • Wolfgang Denk's avatar
      Merge branch 'master' of /home/wd/git/u-boot/custodians · 05f132d7
      Wolfgang Denk authored
      * 'master' of /home/wd/git/u-boot/custodians:
        powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
        powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
        cmd_bdinfo: display the address map size (32-bit vs. 36-bit)
        PowerPC: correct the SATA for p1/p2 rdb-pc platform
        powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
        powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
        powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
        powerpc/corenet_ds: Slave module for boot from SRIO
        powerpc/corenet_ds: Master module for boot from SRIO
        powerpc/corenet_ds: Document for the boot from SRIO
        powerpc/corenet_ds: Correct the compilation errors about ENV
        powerpc/srio: Rewrite the struct ccsr_rio
        powerpc/85xx:Fix lds for nand boot debug info
        powerpc/p2041rdb: add env in NAND support
        powerpc/p2041rdb: add NAND and NAND boot support
        powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
        powerpc/85xx:Avoid vector table compilation for nand_spl
        powerpc/85xx:Fix IVORs addr after vector table relocation
        powerpc/85xx:Avoid hardcoded vector address for IVORs
        powerpc/p1023rds: Disable nor flash node and enable nand flash node
      05f132d7
    • Wolfgang Denk's avatar
      Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx · 5f6db68b
      Wolfgang Denk authored
      * 'master' of git://git.denx.de/u-boot-mpc85xx:
        powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
        powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
        cmd_bdinfo: display the address map size (32-bit vs. 36-bit)
        PowerPC: correct the SATA for p1/p2 rdb-pc platform
        powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
        powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
        powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
        powerpc/corenet_ds: Slave module for boot from SRIO
        powerpc/corenet_ds: Master module for boot from SRIO
        powerpc/corenet_ds: Document for the boot from SRIO
        powerpc/corenet_ds: Correct the compilation errors about ENV
        powerpc/srio: Rewrite the struct ccsr_rio
        powerpc/85xx:Fix lds for nand boot debug info
        powerpc/p2041rdb: add env in NAND support
        powerpc/p2041rdb: add NAND and NAND boot support
        powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
        powerpc/85xx:Avoid vector table compilation for nand_spl
        powerpc/85xx:Fix IVORs addr after vector table relocation
        powerpc/85xx:Avoid hardcoded vector address for IVORs
        powerpc/p1023rds: Disable nor flash node and enable nand flash node
      5f6db68b
    • Wolfgang Denk's avatar
      Merge branch 'master' of /home/wd/git/u-boot/custodians · 3f8550c5
      Wolfgang Denk authored
      * 'master' of /home/wd/git/u-boot/custodians:
        i2c:designware Turn off the ctrl when setting the speed
        i2c: Add support for designware i2c controller
        sh: i2c: Add support I2C controller of SH7734
      3f8550c5
    • Wolfgang Denk's avatar
      Merge branch 'master' of git://git.denx.de/u-boot-i2c · 04a9cb8c
      Wolfgang Denk authored
      * 'master' of git://git.denx.de/u-boot-i2c:
        i2c:designware Turn off the ctrl when setting the speed
        i2c: Add support for designware i2c controller
        sh: i2c: Add support I2C controller of SH7734
      04a9cb8c
    • Wolfgang Denk's avatar
      Merge branch 'master' of /home/wd/git/u-boot/custodians · 0cdf37ba
      Wolfgang Denk authored
      * 'master' of /home/wd/git/u-boot/custodians:
        Blackfin: bfin_sdh: drop dos part hardcode
        Blackfin: move gd/bd to bss by default
        Blackfin: gd_t: relocate volatile markings
      0cdf37ba
    • Wolfgang Denk's avatar
      Merge branch 'master' of git://git.denx.de/u-boot-blackfin · 99310d14
      Wolfgang Denk authored
      * 'master' of git://git.denx.de/u-boot-blackfin:
        Blackfin: bfin_sdh: drop dos part hardcode
        Blackfin: move gd/bd to bss by default
        Blackfin: gd_t: relocate volatile markings
      99310d14
    • Mike Frysinger's avatar
      image/fit: drop inline markings on parser code · 314f634b
      Mike Frysinger authored
      
      
      Putting "inline" on extern funcs makes no sense, so drop them.
      
      Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
      314f634b
    • Wolfgang Denk's avatar
      Merge branch 'master' of git://git.denx.de/u-boot-nds32 · 48680493
      Wolfgang Denk authored
      * 'master' of git://git.denx.de/u-boot-nds32:
        board/adp-ag102: add configuration of adp-ag102
        board/adp-ag102: add board specific files
        nds32/ag102: add ag102 soc support
        nds32/ag102: add header support of ag102 soc
      48680493
    • Vikram Narayanan's avatar
      patman: Change the location of patman path · 330a091c
      Vikram Narayanan authored
      
      
      Fix the location of patman path in README
      
      Signed-off-by: default avatarVikram Narayanan <vikram186@gmail.com>
      Cc: Simon Glass <sjg@chromium.org>
      330a091c
    • Vikram Narayanan's avatar
      patman: Fix a typo error · 1713247f
      Vikram Narayanan authored
      
      
      Signed-off-by: default avatarVikram Narayanan <vikram186@gmail.com>
      Cc: Simon Glass <sjg@chromium.org>
      Acked-by: default avatarSimon Glass <sjg@chromium.org>
      1713247f
  2. 29 Apr, 2012 3 commits
    • Marek Vasut's avatar
      GCC47: Fix warning in md5.c · b68d63ce
      Marek Vasut authored
      
      
      md5.c: In function ‘MD5Final’:
      md5.c:156:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
      md5.c:157:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Wolfgang Denk <wd@denx.de>
      Acked-by: default avatarMike Frysinger <vapier@gentoo.org>
      b68d63ce
    • Marek Vasut's avatar
      GCC47: Fix warning in cmd_nand.c · f624dd15
      Marek Vasut authored
      
      
      cmd_nand.c: In function ‘arg_off_size’:
      cmd_nand.c:216:5: warning: ‘maxsize’ may be used uninitialized in this function [-Wmaybe-uninitialized]
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Scott Wood <scottwood@freescale.com>
      Cc: Wolfgang Denk <wd@denx.de>
      f624dd15
    • Wolfgang Denk's avatar
      Merge branch 'marex@denx.de' of git://git.denx.de/u-boot-staging · e654fac2
      Wolfgang Denk authored
      * 'marex@denx.de' of git://git.denx.de/u-boot-staging:
        CMD: CONFIG_CMD_SETECPR -> CONFIG_CMD_SETEXPR on omap3_logic
        CMD: Fix CONFIG_CMD_SAVEBP_WRITE_SIZE -> CONFIG_CMD_SPL_WRITE_SIZE
        CMD: Fix typo CMD_FSL -> CMD_MFSL in readme
        HWW1U1A: Fix CMD_SHA1 -> CMD_SHA1SUM
        CMD: Remove CMD_LOG, it's unused
        CMD: Fix typo KGBD -> KGDB on debris board
        CMD: Drop CONFIG_CMD_EMMC, it's not used
        CMD: Drop CONFIG_CMD_DFL, it's not used
        CMD: Drop CMD_DCR, it's not used
        CMD: Drop CMD_CAN, it's not used
        CMD: Remove CMD_AUTOSCRIPT, it's not used
        AT91: Drop AT91_SPIMUX command from cmd_all
      e654fac2
  3. 25 Apr, 2012 21 commits
    • Wolfgang Denk's avatar
      Prepare v2012.04.01 · 415d3868
      Wolfgang Denk authored
      
      
      Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
      415d3868
    • Timur Tabi's avatar
      powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR · 822ad60f
      Timur Tabi authored
      
      
      The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but
      that register does not exist on e500v1.
      
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      822ad60f
    • Timur Tabi's avatar
      powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot · 5d065c3e
      Timur Tabi authored
      
      
      Most 85xx boards can be built as a 32-bit or a 36-bit.  Current code sometimes
      displays which of these is actually built, but it's inconsistent.  This is
      especially problematic since the "default" build for a given 85xx board can
      be either one, so if you don't see a message, you can't always know which
      size is being used.  Not only that, but each board includes code that displays
      the message, so there is duplication.
      
      The 'bdinfo' command has been updated to display this information, so
      we don't need to display it at boot time.  The board-specific code is
      deleted.
      
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      5d065c3e
    • Timur Tabi's avatar
      cmd_bdinfo: display the address map size (32-bit vs. 36-bit) · 34e210f5
      Timur Tabi authored
      
      
      Some Freescale SOCs support 32-bit and 36-bit physical addressing, and
      U-Boot must be built to enable one or the other.  Add this information
      to the bdinfo command.
      
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      34e210f5
    • Jerry Huang's avatar
      PowerPC: correct the SATA for p1/p2 rdb-pc platform · befb7d9f
      Jerry Huang authored
      
      
      For p1/p2 rdb-pc platform, use the PCIe-SATA Silicon Image SATA controller.
      Therefore, the SATA driver will use sata_sil, instead sata_sil3114.
      
      Signed-off-by: default avatarJerry Huang <Chang-Ming.Huang@freescale.com>
      CC: Andy Fleming <afleming@gmail.com>
      befb7d9f
    • Liu Gang's avatar
      powerpc/corenet_ds: Slave core in holdoff when boot from SRIO · 5056c8e0
      Liu Gang authored
      
      
      When boot from SRIO, slave's core can be in holdoff after powered on for
      some specific requirements. Master can release the slave's core at the
      right time by SRIO interface.
      
      Master needs to:
      	1. Set outbound SRIO windows in order to configure slave's registers
      	   for the core's releasing.
      	2. Check the SRIO port status when release slave core, if no errors,
      	   will implement the process of the slave core's releasing.
      Slave needs to:
      	1. Set all the cores in holdoff by RCW.
      	2. Be powered on before master's boot.
      
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
      5056c8e0
    • Liu Gang's avatar
      powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO · 0a85a9e7
      Liu Gang authored
      
      
      When boot from SRIO, slave's ENV can be stored in master's memory space,
      then slave can fetch the ENV through SRIO interface.
      
      NOTE: Because the slave can not erase, write master's NOR flash by SRIO
      	  interface, so it can not modify the ENV parameters stored in
      	  master's NOR flash using "saveenv" or other commands.
      
      Master needs to:
      	1. Put the slave's ENV into it's own memory space.
      	2. Set an inbound SRIO window covered slave's ENV stored in master's
      	   memory space.
      Slave needs to:
      	1. Set a specific TLB entry in order to fetch ucode and ENV from master.
      	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.
      
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
      0a85a9e7
    • Liu Gang's avatar
      powerpc/corenet_ds: Slave uploads ucode when boot from SRIO · 3f1af81b
      Liu Gang authored
      
      
      When boot from SRIO, slave's ucode can be stored in master's memory space,
      then slave can fetch the ucode image through SRIO interface. For the
      corenet platform, ucode is for Fman.
      
      Master needs to:
      	1. Put the slave's ucode image into it's own memory space.
      	2. Set an inbound SRIO window covered slave's ucode stored in master's
      	   memory space.
      Slave needs to:
      	1. Set a specific TLB entry in order to fetch ucode from master.
      	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.
      
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
      3f1af81b
    • Liu Gang's avatar
      powerpc/corenet_ds: Slave module for boot from SRIO · 292dc6c5
      Liu Gang authored
      
      
      For the powerpc processors with SRIO interface, boot location can be configured
      from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
      for u-boot image. The image can be fetched from another processor's memory
      space by SRIO link connected between them.
      
      The processor boots from SRIO is slave, the processor boots from normal flash
      memory space and can help slave to boot from its memory space is master.
      They are different environments and requirements:
      
      master:
      	1. NOR flash for its own u-boot image, ucode and ENV space.
      	2. Slave's u-boot image in master NOR flash.
      	3. Normally boot from local NOR flash.
      	4. Configure SRIO switch system if needed.
      slave:
      	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
      	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
      	3. RCW should configure the SerDes, SRIO interfaces correctly.
      	4. Slave must be powered on after master's boot.
      	5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
      	   locally.
      
      For the slave module, need to finish these processes:
      	1. Set the boot location to SRIO1 or SRIO2 by RCW.
          2. Set a specific TLB entry for the boot process.
      	3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
      	4. Slave's u-boot image should be generated specifically by
      	   make xxxx_SRIOBOOT_SLAVE_config.
      	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
      
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
      292dc6c5
    • Liu Gang's avatar
      powerpc/corenet_ds: Master module for boot from SRIO · 5ffa88ec
      Liu Gang authored
      
      
      For the powerpc processors with SRIO interface, boot location can be configured
      from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
      for u-boot image. The image can be fetched from another processor's memory
      space by SRIO link connected between them.
      
      The processor boots from SRIO is slave, the processor boots from normal flash
      memory space and can help slave to boot from its memory space is master.
      They are different environments and requirements:
      
      master:
      	1. NOR flash for its own u-boot image, ucode and ENV space.
      	2. Slave's u-boot image in master NOR flash.
      	3. Normally boot from local NOR flash.
      	4. Configure SRIO switch system if needed.
      slave:
      	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
      	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
      	3. RCW should configure the SerDes, SRIO interfaces correctly.
      	4. Slave must be powered on after master's boot.
      
      For the master module, need to finish these processes:
      	1. Initialize the SRIO port and address space.
      	2. Set inbound SRIO windows covered slave's u-boot image stored in
      	   master's NOR flash.
      	3. Master's u-boot image should be generated specifically by
      	   make xxxx_SRIOBOOT_MASTER_config
      	4. Master must boot first, and then slave can be powered on.
      
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
      5ffa88ec
    • Liu Gang's avatar
      powerpc/corenet_ds: Document for the boot from SRIO · 006f37f6
      Liu Gang authored
      
      
      This document describes the implementation of the boot from SRIO,
      includes the introduction of envionment, an example based on P4080DS
      platform, an example of the slave's RCW, and the description about
      how to use this feature.
      
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      006f37f6
    • Liu Gang's avatar
      powerpc/corenet_ds: Correct the compilation errors about ENV · fd0451e4
      Liu Gang authored
      
      
      When defined CONFIG_ENV_IS_NOWHERE, there will be some
      compilation errors:
      
      ./common/env_nowhere.o: In function `env_relocate_spec':
      ./common/env_nowhere.c:38: multiple definition of `env_relocate_spec'
      ./common/env_flash.o: ./common/env_flash.c:326: first defined here
      ./common/env_nowhere.o: In function `env_get_char_spec':
      ./common/env_nowhere.c:42: multiple definition of `env_get_char_spec'
      ./common/env_flash.o:./common/env_flash.c:78: first defined here
      ./common/env_nowhere.o: In function `env_init':
      ./common/env_nowhere.c:51: multiple definition of `env_init'
      ./common/env_flash.o:./common/env_flash.c:237: first defined here
      make[1]: *** [./common/libcommon.o] Error 1
      make[1]: Leaving directory `./common'
      make: *** [./common/libcommon.o] Error 2
      
      Remove the CONFIG_ENV_IS_IN_FLASH if defined CONFIG_ENV_IS_NOWHERE.
      
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      fd0451e4
    • Liu Gang's avatar
      powerpc/srio: Rewrite the struct ccsr_rio · 7d67ed58
      Liu Gang authored
      
      
      Rewrite this struct for the support of two ports and two message
      units registers.
      
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      7d67ed58
    • Prabhakar Kushwaha's avatar
      powerpc/85xx:Fix lds for nand boot debug info · 5113ee70
      Prabhakar Kushwaha authored
      
      
      Currently "u-boot", the elf file generated via u-boot-nand.lds does not
      contain required debug information i.e. .debug_{line, info, abbrev, aranges,
      ranges} into their respective _global_ sections.
      
      The original ld script line arch/powerpc/cpu/mpc85xx/start.o
      KEEP(*(.bootpg)) is not entirely correct because the start.o file is already
      processed by the linker,therefore the file wildcard in "KEEP(*(.bootpg))" will
      not process start.o again for bootpg.
      
      So Fix u-boot-nand.lds to generate these debug information.
      
      Signed-off-by: default avatarAnmol Paralkar <b07584@freescale.com>
      Signed-off-by: default avatarJohn Russo <John.Russo@freescale.com>
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      5113ee70
    • Shaohui Xie's avatar
      powerpc/p2041rdb: add env in NAND support · 15c8c6c2
      Shaohui Xie authored
      
      
      Add env in NAND support when boot from NAND.
      
      Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      15c8c6c2
    • Shaohui Xie's avatar
      powerpc/p2041rdb: add NAND and NAND boot support · c9b2feaf
      Shaohui Xie authored
      
      
      New P2041RDB board will add a NAND chip, so add support for NAND and
      NAND boot.
      
      Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      c9b2feaf
    • York Sun's avatar
      powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards · 1ba62f10
      York Sun authored
      
      
      P1010RDB and p1_pc_rdb_pc has incorrect configuration for
      CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
      Incorrect setting causes DDR failure in case of SPD absent.
      
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      1ba62f10
    • Prabhakar Kushwaha's avatar
      powerpc/85xx:Avoid vector table compilation for nand_spl · 119a55f9
      Prabhakar Kushwaha authored
      
      
      NAND SPL code never compile the vector table.
      So no need to setup interrupt vector table for NAND SPL.
      
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      119a55f9
    • Prabhakar Kushwaha's avatar
      powerpc/85xx:Fix IVORs addr after vector table relocation · 64829baf
      Prabhakar Kushwaha authored
      
      
      After relocation of vector table in SDRAM's lower address, IVORs value should
      be updated with new handler addresses.
      
      As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs
      are updated with 0x100, 0x200,....f00  hard-coded values.
      
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      64829baf
    • Prabhakar Kushwaha's avatar
      powerpc/85xx:Avoid hardcoded vector address for IVORs · a4107f86
      Prabhakar Kushwaha authored
      
      
      For e500 and e500v2 architecturees processor IVPR address should be alinged on
      64K boundary.
      
      in start.S, CONFIG_SYS_MONITOR_BASE is stored blindly in IVPR assuming it to be
      64K aligned. It may not be true always. If it is not aligned, IVPR + IVORs may
      not point to an exception handler.
      
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      a4107f86
    • Chunhe Lan's avatar
      powerpc/p1023rds: Disable nor flash node and enable nand flash node · 617e46e3
      Chunhe Lan authored
      
      
      In the p1023rds, when system boots from nor flash, kernel only accesses nor
      flash and can not access nand flash with BR0/OR0; when system boots from
      nand flash, kernel only accesses nand flash and can not access nor flash
      with BR0/OR0.
      
      Default device tree nor and nand node should have the following structure:
      
      	Example:
      
      		nor_flash: nor@0,0 {
      			#address-cells = <1>;
      			#size-cells = <1>;
      			compatible = "cfi-flash";
      			reg = <0x0 0x0 0x02000000>;
      			bank-width = <2>;
      			device-width = <1>;
      			status = "okay";
      
      			partition@0 {
      				label = "ramdisk";
      				reg = <0x00000000 0x01c00000>;
      			};
      		}
      
      		nand_flash: nand@1,0 {
      			#address-cells = <1>;
      			#size-cells = <1>;
      			compatible = "fsl,p1023-fcm-nand",
      				     "fsl,elbc-fcm-nand";
      			reg = <0x2 0x0 0x00040000>;
      			status = "disabled";
      
      			u-boot-nand@0 {
      				/* This location must not be altered  */
      				/* 1MB for u-boot Bootloader Image */
      				reg = <0x0 0x00100000>;
      				read-only;
      			};
      		}
      
      When booting from nor flash, the status of nor node is enabled and the
      status of nand node is disabled in the default dts file, so do not do
      anything.
      
      But, when booting from nand flash, need to do some operations:
      
      	o Disable the NOR node by setting status = "disabled";
      	o Enable the NAND node by setting status = "okay";
      
      Signed-off-by: default avatarChunhe Lan <Chunhe.Lan@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      617e46e3
  4. 24 Apr, 2012 3 commits
  5. 23 Apr, 2012 2 commits