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    • York Sun's avatar
      ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC · 2f78eae5
      York Sun authored
      
      
      Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
      ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
      to support memory map and cache attribute for these SoCs. MMU and cache
      are enabled very early to bootst performance, especially for early
      development on emulators. After u-boot relocates to DDR, a new MMU
      table with QBMan cache access is created in DDR. SMMU pagesize is set
      in SMMU_sACR register. Both DDR3 and DDR4 are supported.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarVarun Sethi <Varun.Sethi@freescale.com>
      Signed-off-by: default avatarArnab Basu <arnab.basu@freescale.com>
      2f78eae5