1. 06 Jun, 2014 23 commits
    • Lokesh Vutla's avatar
      ARM: AM43xx: Fix mmcboot command in EXTRA_ENV_SETTINGS · fa03834f
      Lokesh Vutla authored
      loadbootenv expects devtype variable to be set. This is missing in
      mmcboot command. With this the following error comes:
      U-Boot# run mmcboot
      mmc0 is current device
      SD/MMC found on device 0
      ** Bad device usb 0 **
      ** Bad device usb 0 **
      Fixing this by setting devtype as mmc.
      Reported-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      fa03834f
    • Jeroen Hofstee's avatar
      tam3517: fix NAND detection · 0970051d
      Jeroen Hofstee authored
      commit a0a37183 "ARM: omap: merge GPMC initialization code for
      all platform" needs CONFIG_NOR, CONFIG_NAND or CONFIG_CMD_ONENAND
      to be set to access flash. Add CONFIG_NAND for tam3517 derived
      boards to prevent the following error: "nand: error: Unable to
      find NAND settings in GPMC Configuration - quitting"
      
      cc: Stefano Babic <sbabic@denx.de>
      Signed-off-by: default avatarJeroen Hofstee <jeroen@myspectrum.nl>
      0970051d
    • WingMan Kwok's avatar
      keystone: k2hk: enable support of nand ecclayout command · 1dbb64dc
      WingMan Kwok authored
      Enable support of nand ecclayout command.
      Acked-By: default avatarMurali Karicheri <m-karicheri2@ti.com>
      Acked-by: default avatarVitaly Andrianov <vitalya@ti.com>
      Signed-off-by: default avatarWingMan Kwok <w-kwok2@ti.com>
      Signed-off-by: default avatarIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
      1dbb64dc
    • Murali Karicheri's avatar
      keystone: init: enable UART1 to be able use it from kernel · afee59cd
      Murali Karicheri authored
      Currently PWREMU_MGMT is not configured in the Linux generic UART
      driver as this register seems to be specific TI UART IP. So this
      needs to be enabled in u-boot to use UART1 from kernel space.
      Acked-By: default avatarVitaly Andrianov <vitalya@ti.com>
      Signed-off-by: default avatarMurali Karicheri <m-karicheri2@ti.com>
      Signed-off-by: default avatarIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
      afee59cd
    • Tom Rini's avatar
      arm:am33xx: Rework s_init and add board_early_init_f · 196311dc
      Tom Rini authored
      With the changes to the i2c framework (and adopting the omap24xx_i2c
      driver to them) we can no longer call i2c functions prior to gd having
      been set and cleared.  When SPL booting, this is handled by setting gd
      to point to SRAM in s_init.  However in the cases where we are loaded
      directly by ROM (memory mapped NOR or QSPI) we need to make use of the
      normal hooks to slightly delay these calls.
      Signed-off-by: default avatarTom Rini <trini@ti.com>
      196311dc
    • Tom Rini's avatar
      arm:am33xx: Make dram_init call sdram_init() in some contexts · 87acf194
      Tom Rini authored
      We have two contexts for booting these platforms.  One is SPL which is
      roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main,
      board_init_f from SPL, ... then U-Boot loads.  The other is a
      memory-mapped XIP case (NOR or QSPI) where we do not run an SPL.  In
      this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init,
      _main, regular board_init_f.
      
      In the first case s_init will set a valid gd and then be able to call
      sdram_init which in many cases will need i2c (which needs a valid gd for
      gd->cur_i2c_bus).  In this second case we must (and are able to and
      should) defer sdram_init() into dram_init() called by board_init_f as gd
      will have been set in _main and cleared in board_init_f.
      Signed-off-by: default avatarTom Rini <trini@ti.com>
      87acf194
    • Sourav Poddar's avatar
      ti: qspi: populate slave device to set flash quad bit. · ce3cc8ec
      Sourav Poddar authored
      The patch populates the slave data which will be used by flash driver to
      set the  flash quad enable bit.
      Signed-off-by: default avatarSourav Poddar <sourav.poddar@ti.com>
      ce3cc8ec
    • Sourav Poddar's avatar
      am43xx_evm: Add qspiboot target · 7a5f71bc
      Sourav Poddar authored
      The ePOS EVM and EVM SK have QSPI as an option to boot.  Add a qspiboot
      target that utilizes QSPI for env and so forth as an example of best
      practices.  As QSPI is booted from directly we need to chang
      CONFIG_SYS_TEXT_BASE.
      
      Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices
      we need to handle that elsewhere, once NAND support is also added.
      Signed-off-by: default avatarSourav Poddar <sourav.poddar@ti.com>
      Signed-off-by: default avatarTom Rini <trini@ti.com>
      7a5f71bc
    • pekon gupta's avatar
      am335x: update README for BCH16 · 867f0304
      pekon gupta authored
      updates documentation with explanation on how to select ECC schemes.
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      867f0304
    • pekon gupta's avatar
      mtd: nand: omap: add support for BCH16_ECC - NAND driver updates · 46840f66
      pekon gupta authored
      This patch add support for BCH16_ECC to omap_gpmc driver.
      
      *need to BCH16 ECC scheme*
      With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes
      Flash devices have become more suspectible to bit-flips. Thus stronger
      ECC schemes are required for protecting the data.
      But stronger ECC schemes have come with larger-sized ECC syndromes which require
      more space in OOB/Spare. This puts constrains like;
      (a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
      (b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
      Due to (b) this scheme can only be used with NAND devices which have enough
      OOB to satisfy following equation:
      OOBsize per page >= 26 * (page-size / 512)
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      46840f66
    • pekon gupta's avatar
      mtd: nand: omap_gpmc: use macro for register definitions · 8d13a730
      pekon gupta authored
      GPMC can support simultaneous processing of 8 512Byte data chunks, in parallel
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      8d13a730
    • pekon gupta's avatar
      omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT · 68128e0a
      pekon gupta authored
      OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros
      to configure GPMC controller for x7 or x8 bit device connected to its interface.
      Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above
      macros can be completely removed.
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      68128e0a
    • pekon gupta's avatar
      mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device bus-width · b80a6603
      pekon gupta authored
      GPMC controller needs to be configured based on bus-width of the NAND device
      connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI
      parameters is not possible in following situations:
      SPL:    SPL NAND drivers does not support ONFI parameter reading.
      U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init()
              which is called before probing for devices, hence any ONFI parameter
              information is not available during GPMC initialization.
      
      Thus, OMAP NAND driver expected board developers to explicitely write GPMC
      configurations specific to NAND device attached on board in board files itself.
      But this was troublesome for board manufacturers as they need to dive into
      lengthy platform & SoC documents to find details of GPMC registers and
      appropriate configurations to get NAND device working.
      
      This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config
      hich indicates that connected NAND device has x16 bus-width. And then based on
      this config GPMC driver itself initializes itself based on NAND bus-width. This
      keeps board developers free from knowing GPMC controller specific internals.
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      b80a6603
    • David Mosberger's avatar
      mtd: nand: fix GET/SET_FEATURES address on 16-bit devices · 6e1899e6
      David Mosberger authored
      As per following Sections in ONFI Spec, GET_FEATURES and SET_FEATURES also need
      byte-addressing on 16-bit devices.
      
      *Section: Target Initialization"
      "The Read ID and Read Parameter Page commands only use the lower 8-bits of the
       data bus. The host shall not issue commands that use a word data width on x16
       devices until the host determines the device supports a 16-bit data bus width
       in the parameter page."
      
      *Section: Bus Width Requirements*
      "When the host supports a 16-bit bus width, only data is transferred at the
       16-bit width. All address and command line transfers shall use only the lower
       8-bits of the data bus. During command transfers, the host may place any value
       on the upper 8-bits of the data bus. During address transfers, the host shall
       set the upper 8-bits of the data bus to 00h."
      
      So porting following commit from linux kernel
          commit e34fcb07a6d57411de6e15a47724fbe92c5caa42
          Author: David Mosberger <davidm@egauge.net>  (preserving authorship)
          mtd: nand: fix GET/SET_FEATURES address on 16-bit devices
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      6e1899e6
    • Brian Norris's avatar
      mtd: nand: force NAND_CMD_READID onto 8-bit bus · 27ce9e42
      Brian Norris authored
      As per following Sections in ONFI Spec, NAND_CMD_READID should use only
      lower 8-bit for transfering command, address and data even on x16 NAND device.
      
      *Section: Target Initialization"
      "The Read ID and Read Parameter Page commands only use the lower 8-bits of the
       data bus. The host shall not issue commands that use a word data width on x16
       devices until the host determines the device supports a 16-bit data bus width
       in the parameter page."
      
      *Section: Bus Width Requirements*
      "When the host supports a 16-bit bus width, only data is transferred at the
       16-bit width. All address and command line transfers shall use only the lower
       8-bits of the data bus. During command transfers, the host may place any value
       on the upper 8-bits of the data bus. During address transfers, the host shall
       set the upper 8-bits of the data bus to 00h."
      
      Thus porting  following commit from linux-kernel to ensure that column address
      is not altered to align to x16 bus when issuing NAND_CMD_READID command.
      
          commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
          mtd: nand: force NAND_CMD_READID onto 8-bit bus
          Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship)
      
          The NAND command helpers tend to automatically shift the column address
          for x16 bus devices, since most commands expect a word address, not a
          byte address. The Read ID command, however, expects an 8-bit address
          (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
          0x20).
      
          This fixes the column address for a few drivers which imitate the
          nand_base defaults.
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      27ce9e42
    • Brian Norris's avatar
      mtd: nand: don't use read_buf for 8-bit ONFI transfers · b9ae609f
      Brian Norris authored
      Porting below commit from linux-tree, preserving original authorship & commit log
      commit bd9c6e99b58255b9de1982711ac9487c9a2f18be
      Author:     Brian Norris <computersforpeace@gmail.com>
      mtd: nand: don't use read_buf for 8-bit ONFI transfers
      
        Use a repeated read_byte() instead of read_buf(), since for x16 buswidth
        devices, we need to avoid the upper I/O[16:9] bits. See the following
        commit for reference:
      
        commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree)
        Author: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
        Date:   Thu Dec 5 22:22:04 2013 +0100
      
            mtd: nand: don't use {read,write}_buf for 8-bit transfers
      
        Now, I think that all barriers to probing ONFI on x16 devices are
        removed, so remove the check from nand_flash_detect_onfi().
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      b9ae609f
    • pekon gupta's avatar
      mtd: nand: omap: fix error-codes returned from omap-elm driver · 3f990dc8
      pekon gupta authored
      This patch
       omap-elm.c: replaces -ve integer value returned during errorneous condition,
                   with proper error-codes.
       omap-gpmc.c: updates omap-gpmc driver to pass error-codes returned from
                   omap-elm driver to upper layers
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      3f990dc8
    • pekon gupta's avatar
      mtd: nand: omap_gpmc: minor cleanup of omap_correct_data_bch · a09431da
      pekon gupta authored
      This patch tries to avoid some local pointer dereferences, by using common
      local variables in omap_correct_data_bch()
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      a09431da
    • pekon gupta's avatar
      mtd: nand: omap_gpmc: rename struct nand_bch_priv to struct omap_nand_info · 9233279f
      pekon gupta authored
      This patch renames 'struct nand_bch_priv' which currently holds private data only
      for BCH ECC schemes, into 'struct omap_nand_info' so that same can be used for
      all ECC schemes
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      9233279f
    • pekon gupta's avatar
      mtd: nand: omap_gpmc: remove unused members of 'struct nand_bch_priv' · d21e77ff
      pekon gupta authored
      This patch prepares to refactor 'struct nand_bch_priv' -> 'struct omap_nand_info'
      And thus performs following clean-ups:
       - remove nand_bch_priv.type: use nand_bch_priv.ecc_scheme instead
       - remove nand_bch_priv.mode: <unused>
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      d21e77ff
    • pekon gupta's avatar
      mtd: nand: omap_elm: use macros for register definitions · 0439d752
      pekon gupta authored
      This patch adds macros for following parameters of ELM Hardware engine
       - ELM_MAX_CHANNELS: ELM can process 8 data streams simultaneously
       - ELM_MAX_ERRORS: ELM can detect upto 16 ECC error when using BCH16 scheme
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      0439d752
    • pekon gupta's avatar
      mtd: nand: omap_elm: use bch_type instead of nibble count to differentiate between BCH4/BCH8/BCH16 · 41bbe4dd
      pekon gupta authored
      ELM hardware engine support ECC error detection for multiple ECC strengths like
       +------+------------------------+
       |Type  | ECC syndrome length    |
       +------+------------------------+
       |BCH4  | 6.5 bytes = 13 nibbles |
       |BCH8  | 13 byte = 26 nibbles   |
       |BCH16 | 26 bytes = 52 nibbles  |
       +------+------------------------+
      
      Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles')
      to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type'
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      41bbe4dd
    • pekon gupta's avatar
      mtd: nand: omap_elm: remove #include omap_gpmc.h · b98c5755
      pekon gupta authored
      There is no dependency of omap_elm.c on omap_gpmc.h
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      b98c5755
  2. 02 Jun, 2014 1 commit
  3. 31 May, 2014 1 commit
  4. 29 May, 2014 1 commit
  5. 28 May, 2014 12 commits
  6. 26 May, 2014 2 commits