- 24 Sep, 2009 21 commits
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Paul Gortmaker authored
The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match the latest codebase and makes use of the new shared PCI functions to reduce board duplication. It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB. Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place) Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Paul Gortmaker authored
Recycle the recently added PCI-e wrapper used to reduce board duplication of code by creating a similar version for plain PCI. Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Paul Gortmaker authored
The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM. Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Paul Gortmaker authored
Sweep throught the board specific file and replace the various register proddings with the equivalent I/O accessors. Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Paul Gortmaker authored
With only eTSEC1 and 2 being brought out to RJ-45 connectors, we aren't interested in the eTSEC3/4 voltage hack on this board Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Paul Gortmaker authored
The sbc8548 has a 64MB SODIMM flash module off of CS6 that previously wasn't enumerated by u-boot. There were already BR6/OR6 settings for it [used by cpu_init_f()] but there was no TLB entry and it wasn't in the list of flash banks reported to u-boot. The location of the 64MB flash is "pulled back" 8MB from a 64MB boundary, in order to allow address space for the 8MB boot flash that is at the end of 32 bit address space. This means creating two 4MB TLB entries for the 8MB chunk, and then expanding the original boot flash entry to 64MB in order to cover the 8MB boot flash and the remainder (56MB) of the user flash. Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Paul Gortmaker authored
Fix the extra long lines to be consistent with u-boot coding style. No functional change here. Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com>
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Paul Gortmaker authored
The get_clock_freq() comes from freescale/common/cadmus.c and is only valid for the CDS based 85xx reference platforms. It would be nice if we could read the 33 vs. 66MHz status somehow, but in the meantime, tie it to CONFIG_SYS_CLK_FREQ like all the other non-CDS boards do. Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Paul Gortmaker authored
There are a couple defines and PCI bridge quirks related to the PCI backplane of the MPC8548CDS that have no meaning in the context of the port to the sbc8548 board, so delete them. Also, the form factor of the sbc8548 is a standalone board with a single PCI-X and a single PCI-e slot. That pretty much guarantees that it will never be a PCI agent itself, so the host/agent and root complex/end node distinctions have been removed. Similarly, since there is no physical connector mapping to PCI2, so all references of PCI2 in the board support files have been removed as well. Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Paul Gortmaker authored
Create a board_eth_init to allow a place to hook in the PCI ethernet init after all the eTSEC are up and configured. Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Poonam Aggrwal authored
The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010 where max DDR data width supported is 64bit. As a next step the DDR data width initialization would be made more dynamic with more flexibility from the board perspective and user choice. Going forward we would also remove the hardcodings for platforms with onboard memories and try to use the FSL SPD code for DDR initialization. Signed-off-by:
Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Paul Gortmaker authored
The previous README.sbc8548 was pretty much content-free. Replace it with something that actually gives the end user some relevant hardware details, and also lists the u-boot configuration choices. Also in the cosmetic department, fix the bogus line in the Makefile that was carried over from the SBC8560 Makefile, and the typo in the sbc8548.c copyright. Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
On 85xx platforms we shouldn't be using any LAWAR_* defines but using the LAW_* ones provided by fsl-law.h. Rename any such uses and limit the LAWAR_ to the 83xx platform as the only user so we will get compile errors in the future. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
General code cleanup to use in/out IO accessors as well as making the code that prints out info sane between board and generic fsl pci code. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Mingkai Hu authored
Signed-off-by:
Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
For some reason the CLKDIV field varies between SoC in how it interprets the bit values. All 83xx and early (e500v1) PQ3 devices support: clk/2: CLKDIV = 2 clk/4: CLKDIV = 4 clk/8: CLKDIV = 8 Newer PQ3 (e500v2) and MPC86xx support: clk/4: CLKDIV = 2 clk/8: CLKDIV = 4 clk/16: CLKDIV = 8 Ensure that the MPC86xx and MPC85xx still get the same behavior and make the defines reflect their logical view (not the value of the field). Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Acked-by:
Peter Tyser <ptyser@xes-inc.com>
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- 23 Sep, 2009 6 commits
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Wolfgang Denk authored
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Wolfgang Denk authored
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Simon Kagstrom authored
This patch adds support for resolving symlinks to directories as well as relative symlinks. Symlinks are now always resolved during file lookup, so the load stage no longer needs to special-case them. Signed-off-by:
Simon Kagstrom <simon.kagstrom@netinsight.net> Signed-off-by:
Stefan Roese <sr@denx.de>
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Rupjyoti Sarmah authored
u-boot reports a PCIE PLL lock error at boot time on Yucca board, and left PCIe nonfunctional. This is fixed by making u-boot function ppc4xx_init_pcie() to wait 300 uS after negating reset before the first check of the PLL lock. Signed-off-by:
Rupjyoti Sarmah <rsarmah@amcc.com> Signed-off-by:
Stefan Roese <sr@denx.de>
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Dirk Eibach authored
DDR2 timing for intip was on the edge for some of the available chips for this board. Now it is verfied to work with all of them. Signed-off-by:
Dirk Eibach <eibach@gdsys.de> Signed-off-by:
Stefan Roese <sr@denx.de>
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- 22 Sep, 2009 6 commits
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Wolfgang Denk authored
Fix warning: ide.c:60: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by:
Wolfgang Denk <wd@denx.de> Cc: Guennadi Liakhovetski <lg@denx.de>
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Peter Tyser authored
Remove board-specific #ifdefs for calling phy_reset() during initializtion Signed-off-by:
Peter Tyser <ptyser@xes-inc.com>
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Peter Tyser authored
Remove board-specific #ifdefs for calling misc_init_r() during initializtion Signed-off-by:
Peter Tyser <ptyser@xes-inc.com> Acked-by:
Heiko Schocher <hs@denx.de>
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Peter Tyser authored
The more standard 'source' command provides identical functionality to the autoscr command. Environment variable names/values on the MVBC_P, MVBML7, kmeter1, mgcoge, and km8xx boards are updated to no longer refernce 'autoscr'. The 'autoscript' and 'autoscript_uname' environment variables are also removed. Signed-off-by:
Peter Tyser <ptyser@xes-inc.com> Acked-by:
Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by:
Heiko Schocher <hs@denx.de>
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Paul Gibson authored
Micron nand flash needs a reset before a read command is issued. The current mpc5121_nfc driver ignores the reset command.
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Marcel Ziswiler authored
Signed-off-by:
Marcel Ziswiler <marcel.ziswiler@noser.com> Acked-by:
Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by:
Heiko Schocher <hs@denx.de>
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- 18 Sep, 2009 2 commits
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Wolfgang Denk authored
Fix warning: flash.c:531: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by:
Wolfgang Denk <wd@denx.de> Cc: Kri Davsson <kd@flaga.is>
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Wolfgang Denk authored
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- 17 Sep, 2009 5 commits
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Simon Kagstrom authored
Commits 02f99901 52d61227 introduced a regression where platform-specific ffs/fls implementations were defined away. This patch corrects that by using PLATFORM_xxx instead of the name itself. Signed-off-by:
Simon Kagstrom <simon.kagstrom@netinsight.net> Acked-by:
Kumar Gala <galak@kernel.crashing.org> Acked-by:
Stefan Roese <sr@denx.de>
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Stefan Roese authored
All 4xx variants had their own, mostly identical get_OPB_freq() function. Some variants even only had the OPB frequency calculated in this routine and not supplied the sys_info.freqOPB variable correctly (e.g. 405EZ). This resulted in incorrect OPB values passed via the FDT to Linux. This patch now removes all those copies and only uses one function for all 4xx variants (except for IOP480 which doesn't have an OPB). Signed-off-by:
Stefan Roese <sr@denx.de>
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Stefan Roese authored
Acadia still used the "old" arch/ppc bootm commands for booting Linux images without FDT. This patch now enables these fdt-aware boot commands for Acadia as well. Signed-off-by:
Stefan Roese <sr@denx.de>
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Stefan Roese authored
With this fix, Linux correctly configures the baudrate when booting with FDT passed from U-Boot to Linux. Signed-off-by:
Stefan Roese <sr@denx.de>
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