fsl_mdio.h 1.94 KB
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/*
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 * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc.
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 *	Jun-jie Zhang <b18070@freescale.com>
 *	Mingkai Hu <Mingkai.hu@freescale.com>
 *
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 * SPDX-License-Identifier:	GPL-2.0+
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 */
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#ifndef __FSL_PHY_H__
#define __FSL_PHY_H__

#include <net.h>
#include <miiphy.h>
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struct tsec_mii_mng {
	u32 miimcfg;		/* MII management configuration reg */
	u32 miimcom;		/* MII management command reg */
	u32 miimadd;		/* MII management address reg */
	u32 miimcon;		/* MII management control reg */
	u32 miimstat;		/* MII management status reg  */
	u32 miimind;		/* MII management indication reg */
	u32 ifstat;		/* Interface Status Register */
};

int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
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/* PHY register offsets */
#define PHY_EXT_PAGE_ACCESS	0x1f

/* MII Management Configuration Register */
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#define MIIMCFG_RESET_MGMT		0x80000000
#define MIIMCFG_MGMT_CLOCK_SELECT	0x00000007
#define MIIMCFG_INIT_VALUE		0x00000003
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/* MII Management Command Register */
#define MIIMCOM_READ_CYCLE	0x00000001
#define MIIMCOM_SCAN_CYCLE	0x00000002

/* MII Management Address Register */
#define MIIMADD_PHY_ADDR_SHIFT	8

/* MII Management Indicator Register */
#define MIIMIND_BUSY		0x00000001
#define MIIMIND_NOTVALID	0x00000004

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void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
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		int dev_addr, int reg, int value);
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int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
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		int dev_addr, int regnum);
int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
		u16 value);
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int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
		int regnum, u16 value);
int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
		int regnum);
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struct fsl_pq_mdio_info {
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	struct tsec_mii_mng __iomem *regs;
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	char *name;
};
int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);

#endif /* __FSL_PHY_H__ */