fsl_ddr_dimm_params.h 2.94 KB
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/*
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 * Copyright 2008-2014 Freescale Semiconductor, Inc.
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 *
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 * SPDX-License-Identifier:	GPL-2.0
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 */

#ifndef DDR2_DIMM_PARAMS_H
#define DDR2_DIMM_PARAMS_H

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#define EDC_DATA_PARITY	1
#define EDC_ECC		2
#define EDC_AC_PARITY	4

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/* Parameters for a DDR dimm computed from the SPD */
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typedef struct dimm_params_s {

	/* DIMM organization parameters */
	char mpart[19];		/* guaranteed null terminated */

	unsigned int n_ranks;
	unsigned long long rank_density;
	unsigned long long capacity;
	unsigned int data_width;
	unsigned int primary_sdram_width;
	unsigned int ec_sdram_width;
	unsigned int registered_dimm;
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	unsigned int device_width;	/* x4, x8, x16 components */
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	/* SDRAM device parameters */
	unsigned int n_row_addr;
	unsigned int n_col_addr;
	unsigned int edc_config;	/* 0 = none, 1 = parity, 2 = ECC */
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#ifdef CONFIG_SYS_FSL_DDR4
	unsigned int bank_addr_bits;
	unsigned int bank_group_bits;
#else
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	unsigned int n_banks_per_sdram_device;
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#endif
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	unsigned int burst_lengths_bitmask;	/* BL=4 bit 2, BL=8 = bit 3 */
	unsigned int row_density;

	/* used in computing base address of DIMMs */
	unsigned long long base_address;
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	/* mirrored DIMMs */
	unsigned int mirrored_dimm;	/* only for ddr3 */
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	/* DIMM timing parameters */

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	int mtb_ps;	/* medium timebase ps */
	int ftb_10th_ps; /* fine timebase, in 1/10 ps */
	int taa_ps;	/* minimum CAS latency time */
	int tfaw_ps;	/* four active window delay */
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	/*
	 * SDRAM clock periods
	 * The range for these are 1000-10000 so a short should be sufficient
	 */
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	int tckmin_x_ps;
	int tckmin_x_minus_1_ps;
	int tckmin_x_minus_2_ps;
	int tckmax_ps;
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	/* SPD-defined CAS latencies */
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	unsigned int caslat_x;
	unsigned int caslat_x_minus_1;
	unsigned int caslat_x_minus_2;
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	unsigned int caslat_lowest_derated;	/* Derated CAS latency */

	/* basic timing parameters */
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	int trcd_ps;
	int trp_ps;
	int tras_ps;

#ifdef CONFIG_SYS_FSL_DDR4
	int trfc1_ps;
	int trfc2_ps;
	int trfc4_ps;
	int trrds_ps;
	int trrdl_ps;
	int tccdl_ps;
#else
	int twr_ps;	/* maximum = 63750 ps */
	int trfc_ps;	/* max = 255 ns + 256 ns + .75 ns
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				       = 511750 ps */
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	int trrd_ps;	/* maximum = 63750 ps */
	int twtr_ps;	/* maximum = 63750 ps */
	int trtp_ps;	/* byte 38, spd->trtp */
#endif
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	int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
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	int refresh_rate_ps;
	int extended_op_srt;
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#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
	int tis_ps;	/* byte 32, spd->ca_setup */
	int tih_ps;	/* byte 33, spd->ca_hold */
	int tds_ps;	/* byte 34, spd->data_setup */
	int tdh_ps;	/* byte 35, spd->data_hold */
	int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
	int tqhs_ps;	/* byte 45, spd->tqhs */
#endif
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	/* DDR3 RDIMM */
	unsigned char rcw[16];	/* Register Control Word 0-15 */
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#ifdef CONFIG_SYS_FSL_DDR4
	unsigned int dq_mapping[18];
	unsigned int dq_mapping_ors;
#endif
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} dimm_params_t;

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unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
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					 const generic_spd_eeprom_t *spd,
					 dimm_params_t *pdimm,
					 unsigned int dimm_number);

#endif