kirkwood_spi.c 7.8 KB
Newer Older
1 2 3 4 5 6 7
/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 *
 * Derived from drivers/spi/mpc8xxx_spi.c
 *
8
 * SPDX-License-Identifier:	GPL-2.0+
9 10 11
 */

#include <common.h>
12
#include <dm.h>
13 14
#include <malloc.h>
#include <spi.h>
15
#include <asm/io.h>
16
#include <asm/arch/soc.h>
17
#ifdef CONFIG_KIRKWOOD
18
#include <asm/arch/mpp.h>
19
#endif
20
#include <asm/arch-mvebu/spi.h>
21

22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
static void _spi_cs_activate(struct kwspi_registers *reg)
{
	setbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
}

static void _spi_cs_deactivate(struct kwspi_registers *reg)
{
	clrbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
}

static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
		     const void *dout, void *din, unsigned long flags)
{
	unsigned int tmpdout, tmpdin;
	int tm, isread = 0;

	debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);

	if (flags & SPI_XFER_BEGIN)
		_spi_cs_activate(reg);

	/*
	 * handle data in 8-bit chunks
	 * TBD: 2byte xfer mode to be enabled
	 */
	clrsetbits_le32(&reg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);

	while (bitlen > 4) {
		debug("loopstart bitlen %d\n", bitlen);
		tmpdout = 0;

		/* Shift data so it's msb-justified */
		if (dout)
			tmpdout = *(u32 *)dout & 0xff;

		clrbits_le32(&reg->irq_cause, KWSPI_SMEMRDIRQ);
		writel(tmpdout, &reg->dout);	/* Write the data out */
		debug("*** spi_xfer: ... %08x written, bitlen %d\n",
		      tmpdout, bitlen);

		/*
		 * Wait for SPI transmit to get out
		 * or time out (1 second = 1000 ms)
		 * The NE event must be read and cleared first
		 */
		for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
			if (readl(&reg->irq_cause) & KWSPI_SMEMRDIRQ) {
				isread = 1;
				tmpdin = readl(&reg->din);
				debug("spi_xfer: din %p..%08x read\n",
				      din, tmpdin);

				if (din) {
					*((u8 *)din) = (u8)tmpdin;
					din += 1;
				}
				if (dout)
					dout += 1;
				bitlen -= 8;
			}
			if (isread)
				break;
		}
		if (tm >= KWSPI_TIMEOUT)
			printf("*** spi_xfer: Time out during SPI transfer\n");

		debug("loopend bitlen %d\n", bitlen);
	}

	if (flags & SPI_XFER_END)
		_spi_cs_deactivate(reg);

	return 0;
}

#ifndef CONFIG_DM_SPI

99 100
static struct kwspi_registers *spireg =
	(struct kwspi_registers *)MVEBU_SPI_BASE;
101

102
#ifdef CONFIG_KIRKWOOD
103
static u32 cs_spi_mpp_back[2];
104
#endif
105

106 107 108 109 110
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
				unsigned int max_hz, unsigned int mode)
{
	struct spi_slave *slave;
	u32 data;
111
#ifdef CONFIG_KIRKWOOD
112 113 114 115
	static const u32 kwspi_mpp_config[2][2] = {
		{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
		{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
	};
116
#endif
117 118 119 120

	if (!spi_cs_is_valid(bus, cs))
		return NULL;

121
	slave = spi_alloc_slave_base(bus, cs);
122 123 124
	if (!slave)
		return NULL;

125
	writel(KWSPI_SMEMRDY, &spireg->ctrl);
126 127

	/* calculate spi clock prescaller using max_hz */
128 129 130
	data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
	data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
	data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
131 132 133

	/* program spi clock prescaller using max_hz */
	writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
134
	debug("data = 0x%08x\n", data);
135 136

	writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
137
	writel(KWSPI_IRQMASK, &spireg->irq_mask);
138

139
#ifdef CONFIG_KIRKWOOD
140
	/* program mpp registers to select  SPI_CSn */
141
	kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
142
#endif
143 144 145 146 147 148

	return slave;
}

void spi_free_slave(struct spi_slave *slave)
{
149
#ifdef CONFIG_KIRKWOOD
150
	kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
151
#endif
152 153 154
	free(slave);
}

155 156 157 158
#if defined(CONFIG_SYS_KW_SPI_MPP)
u32 spi_mpp_backup[4];
#endif

159 160 161 162 163
__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
{
	return 0;
}

164 165
int spi_claim_bus(struct spi_slave *slave)
{
166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193
#if defined(CONFIG_SYS_KW_SPI_MPP)
	u32 config;
	u32 spi_mpp_config[4];

	config = CONFIG_SYS_KW_SPI_MPP;

	if (config & MOSI_MPP6)
		spi_mpp_config[0] = MPP6_SPI_MOSI;
	else
		spi_mpp_config[0] = MPP1_SPI_MOSI;

	if (config & SCK_MPP10)
		spi_mpp_config[1] = MPP10_SPI_SCK;
	else
		spi_mpp_config[1] = MPP2_SPI_SCK;

	if (config & MISO_MPP11)
		spi_mpp_config[2] = MPP11_SPI_MISO;
	else
		spi_mpp_config[2] = MPP3_SPI_MISO;

	spi_mpp_config[3] = 0;
	spi_mpp_backup[3] = 0;

	/* set new spi mpp and save current mpp config */
	kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
#endif

194 195 196 197 198
	return board_spi_claim_bus(slave);
}

__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
{
199 200 201 202
}

void spi_release_bus(struct spi_slave *slave)
{
203 204 205
#if defined(CONFIG_SYS_KW_SPI_MPP)
	kirkwood_mpp_conf(spi_mpp_backup, NULL);
#endif
206 207

	board_spi_release_bus(slave);
208 209 210 211 212 213 214 215 216 217
}

#ifndef CONFIG_SPI_CS_IS_VALID
/*
 * you can define this function board specific
 * define above CONFIG in board specific config file and
 * provide the function in board specific src file
 */
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
218
	return bus == 0 && (cs == 0 || cs == 1);
219 220 221
}
#endif

222 223 224 225
void spi_init(void)
{
}

226 227
void spi_cs_activate(struct spi_slave *slave)
{
228
	_spi_cs_activate(spireg);
229 230 231 232
}

void spi_cs_deactivate(struct spi_slave *slave)
{
233
	_spi_cs_deactivate(spireg);
234 235
}

236 237
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
	     const void *dout, void *din, unsigned long flags)
238
{
239 240
	return _spi_xfer(spireg, bitlen, dout, din, flags);
}
241

242
#else
243

244
/* Here now the DM part */
245

246 247 248
struct mvebu_spi_platdata {
	struct kwspi_registers *spireg;
};
249

250 251 252
struct mvebu_spi_priv {
	struct kwspi_registers *spireg;
};
253

254 255 256 257 258
static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
{
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	struct kwspi_registers *reg = plat->spireg;
	u32 data;
259

260 261 262 263
	/* calculate spi clock prescaller using max_hz */
	data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
	data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
	data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
264

265 266 267
	/* program spi clock prescaler using max_hz */
	writel(KWSPI_ADRLEN_3BYTE | data, &reg->cfg);
	debug("data = 0x%08x\n", data);
268

269 270
	return 0;
}
271

272 273 274 275
static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
{
	return 0;
}
276

277 278 279 280 281 282 283 284 285
static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
			  const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);

	return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
}

286 287 288 289 290 291 292 293 294 295 296 297 298
static int mvebu_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);

	/* Configure the chip-select in the CTRL register */
	clrsetbits_le32(&plat->spireg->ctrl,
			KWSPI_CS_MASK << KWSPI_CS_SHIFT,
			spi_chip_select(dev) << KWSPI_CS_SHIFT);

	return 0;
}

299 300 301 302 303 304 305 306
static int mvebu_spi_probe(struct udevice *bus)
{
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
	struct kwspi_registers *reg = plat->spireg;

	writel(KWSPI_SMEMRDY, &reg->ctrl);
	writel(KWSPI_SMEMRDIRQ, &reg->irq_cause);
	writel(KWSPI_IRQMASK, &reg->irq_mask);
307 308 309

	return 0;
}
310

311
static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
312
{
313 314 315 316 317
	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);

	plat->spireg = (struct kwspi_registers *)dev_get_addr(bus);

	return 0;
318
}
319 320

static const struct dm_spi_ops mvebu_spi_ops = {
321
	.claim_bus	= mvebu_spi_claim_bus,
322 323 324 325 326 327 328 329 330 331
	.xfer		= mvebu_spi_xfer,
	.set_speed	= mvebu_spi_set_speed,
	.set_mode	= mvebu_spi_set_mode,
	/*
	 * cs_info is not needed, since we require all chip selects to be
	 * in the device tree explicitly
	 */
};

static const struct udevice_id mvebu_spi_ids[] = {
332
	{ .compatible = "marvell,armada-375-spi" },
333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348
	{ .compatible = "marvell,armada-380-spi" },
	{ .compatible = "marvell,armada-xp-spi" },
	{ }
};

U_BOOT_DRIVER(mvebu_spi) = {
	.name = "mvebu_spi",
	.id = UCLASS_SPI,
	.of_match = mvebu_spi_ids,
	.ops = &mvebu_spi_ops,
	.ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
	.priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
	.probe = mvebu_spi_probe,
};
#endif