README.mpc85xxads 10.1 KB
Newer Older
1 2
Motorola MPC8540ADS and MPC8560ADS board

3 4
Created 10/15/03 Xianghua Xiao
Updated 13-July-2004 Jon Loeliger
5 6
-----------------------------------------

7
0. Toolchain
8 9

    The Binutils in current ELDK toolchain will not support MPC85xx
10
    chip.  You need to use binutils-2.14.tar.bz2 (or newer) from
11 12 13 14 15
    http://ftp.gnu.org/gnu/binutils.

    The 8540/8560 ADS code base is known to compile using:
	gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)

16

17
1. SWITCH SETTINGS & JUMPERS
18

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
1.0 Nomenclature

    For some reason, the HW designers describe the switch settings
    in terms of 0 and 1, and then map that to physical switches where
    the label "On" refers to logic 0 and "Off" (unlabeled) is logic 1.
    Luckily, we're SW types and virtual settings are handled daily.

    The switches for the Rev A board are numbered differently than
    for the Pilot board.  Oh yeah.

    Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
    bits may contribute to signals that are numbered based at 0,
    and some of those signals may be high-bit-number-0 too.  Heed
    well the names and labels and do not get confused.

    "Off" == 1
    "On"  == 0

    SW18 is switch 18 as silk-screened onto the board.
38
    SW4[8] is the bit labeled 8 on Switch 4.
39 40 41 42 43 44
    SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2
    SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3

1.1 For the MPC85xxADS Pilot Board

    First, make sure the board default setting is consistent with the document
45
    shipped with your board. Then apply the following changes:
46
    SW3[1-6]="all OFF"	(boot from 32bit flash, no boot sequence is used)
47
    SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560)
48
    SW11[2]='OFF for 8560, ON for 8540' (toggle 8540.8560 mode)
49
    SW11[7]='ON' (rev2), 'OFF' (rev1)
50 51 52 53
    SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector)
    SW22[1-4]="OFF OFF ON OFF"
    SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF"
    J1 = "Enable Prog" (Make sure your flash is programmable for development)
54

55
    If you want to test PCI functionality with a 33Mhz PCI card, you will
56 57 58
    have to change the system clock from the default 66Mhz to 33Mhz by
    setting SW15[1]="OFF" and SW17[8]="OFF". After that you may also need
    double your platform clock(SW6) because the system clock is now only
59 60
    half of its original value. For example, if at 66MHz your system
    clock showed SW6[0:1] = 01, then at 33MHz SW6[0:1] it should be 10.
61

62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101
	SW17[8] ------+	   SW6
	SW15[1] ----+ |	  [0:1]
		    V V	   V V
	33MHz	    1 1	   1 0
	66MHz	    0 0	   0 1

    Hmmm... That SW6 setting description is incomplete but it works.


1.3 For the MPC85xxADS Rev A Board

    As shipped, the board should be a 33MHz PCI bus with a CPU Clock
    rate of 825 +/- fuzz:

	Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC:	82 MHz

    For 33MHz PCI, the switch settings should be like this:

	SW18[7:1] = 0100001 = M==33 =>	  33MHz
	SW18[8]	  =	  1	    => PWD Divider == 16
	SW16[1:2] =	 11	    => N == 16 as PWD==1

    Use the magical formula:
	Fout (MHz) = 16 * M / N = 16 * 33 / 16 = 33 MHz

	SW7[1:4]  =    1010 = 10    => 10 x 33	 = 330	CCB Sysclk
	SW7[5:6]  =	 01	    => 5:2 x 330 = 825	Core clock


    For 66MHz PCI, the switch settings should be like this:

	SW18[7:1] = 0100001 = M==33 =>	  33MHz
	SW18[8]	  =	  0	    => PWD Divider == 1
	SW16[1:2] =	 01	    => N == 8 as PWD == 0

    Use the magical formula:
	Fout (MHz) = 16 * M / N = 16 * 33 / 8 = 66 MHz

	SW7[1:4]  =    0101 =  5    => 5 x 66	 = 330	CCB Sysclk
	SW7[5:6]  =	 01	    => 5:2 x 330 = 825	Core clock
102

103 104 105
    In order to use PCI-X (only in the first PCI slot.  The one with
    the RIO connector), you need to set SW1[4] (config) to 1 (off).
    Also, configure the board to run PCI at 66 MHz.
106 107

2. MEMORY MAP TO WORK WITH LINUX KERNEL
108 109

2.1. For the initial bringup, we adopted a consistent memory scheme
110
     between U-Boot and linux kernel, you can customize it based on your
111 112
     system requirements:

113 114 115 116 117 118 119 120
     0x0000_0000     0x7fff_ffff     DDR		     2G
     0x8000_0000     0x9fff_ffff     PCI MEM		     512M
     0xc000_0000     0xdfff_ffff     Rapid IO		     512M
     0xe000_0000     0xe00f_ffff     CCSR		     1M
     0xe200_0000     0xe2ff_ffff     PCI IO		     16M
     0xf000_0000     0xf7ff_ffff     SDRAM		     128M
     0xf800_0000     0xf80f_ffff     BCSR		     1M
     0xff00_0000     0xffff_ffff     FLASH (boot bank)	     16M
121 122 123 124 125 126

2.2 We are submitting Linux kernel patches for MPC8540 and MPC8560. You
    can download them from linuxppc-2.4 public source. Please make sure the
    kernel's ppcboot.h is consistent with U-Boot's u-boot.h. You can use two
    default configuration files as your starting points to configure the
    kernel:
127 128
	arch/powerpc/configs/mpc8540_ads_defconfig
	arch/powerpc/configs/mpc8560_ads_defconfig
129 130

3. DEFINITIONS AND COMPILATION
131

132 133 134 135
3.1 Explanation on NEW definitions in:
	include/configs/MPC8540ADS.h
	include/configs/MPC8560ADS.h

136
    CONFIG_BOOKE	    BOOKE(e.g. Motorola MPC85xx, AMCC 440, etc)
137 138 139 140 141 142 143 144
    CONFIG_E500		    BOOKE e500 family(Motorola)
    CONFIG_MPC85xx	    MPC8540,MPC8560 and their derivatives
    CONFIG_MPC8540	    MPC8540 specific
    CONFIG_MPC8540ADS	    MPC8540ADS board specific
    CONFIG_MPC8560ADS	    MPC8560ADS board specific
    CONFIG_TSEC_ENET	    Use on-chip 10/100/1000 ethernet for networking
    CONFIG_SPD_EEPROM	    Use SPD EEPROM for DDR auto configuration, you can
			    also manual config the DDR after undef this
145
			    definition.
146
    CONFIG_DDR_ECC	    only for ECC DDR module
147 148
    CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN	    DLL fix on some ADS boards needed
			    for more stability.
149
    CONFIG_HAS_FEC	    If an FEC is on chip, set to 1, else 0.
150 151 152 153

Other than the above definitions, the rest in the config files are
straightforward.

154 155 156

3.2 Compilation

157 158 159 160 161 162 163
    Assuming you're using BASH shell:

	export CROSS_COMPILE=your-cross-compile-prefix
	cd u-boot
	make distclean
	make MPC8560ADS_config (or make MPC8540ADS_config)
	make
164

165
4.  Notes:
166

167
4.1 When connecting with kermit, the following commands must be present.in
168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193
    your .kermrc file. These are especially important when booting as
    MPC8560, as the serial console will not work without them:

	set speed 115200
	set carrier-watch off
	set handshake none
	set flow-control none
	robust


4.2 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC
    ethernet. If that happens, you can try the following steps to make
    network work:

	MPC8560ADS>tftp 1000000 pImage
	(if it hangs, use Ctrl-C to quit)
	MPC8560ADS>nm fdf24524
	>0
	>1
	>. (to quit this memory operation)
	MPC8560ADS>tftp 1000000 pImage

4.3 If you're one of the early developers using the Rev1 8540/8560 chips,
    please use U-Boot 1.0.0, as the newer silicon will only support Rev2
    and future revisions of 8540/8560.

194

195
4.4 Reflash U-Boot Image using U-Boot
196

197 198 199 200
    tftp 10000 u-boot.bin
    protect off fff80000 ffffffff
    erase fff80000 ffffffff
    cp.b 10000 fff80000 80000
201

202

203
4.5 Reflash U-Boot with a BDI-2000
204

205
    BDI> erase 0xFFF80000 0x4000 0x20
206 207 208 209
    BDI> prog 0xfff80000 u-boot.bin.8560ads
    BDI> verify


210
5. Screen dump MPC8540ADS board
211

212 213 214 215 216 217 218 219 220
U-Boot 1.1.2(pq3-20040707-0) (Jul  6 2004 - 17:34:25)

Freescale PowerPC
    Core: E500, Version: 2.0, (0x80200020)
    System: 8540, Version: 2.0, (0x80300020)
    Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC:  82 MHz
    L1 D-cache 32KB, L1 I-cache 32KB enabled.
Board: ADS
    PCI1: 32 bit, 66 MHz (compiled)
221
I2C:   ready
222 223 224
DRAM:  Initializing
    SDRAM: 64 MB
    DDR: 256 MB
225 226 227 228 229 230 231
FLASH: 16 MB
L2 cache enabled: 256KB
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
232 233 234 235
Net:   MOTO ENET0: PHY is Marvell 88E1011S (1410c62)
MOTO ENET1: PHY is Marvell 88E1011S (1410c62)
MOTO ENET2: PHY is Davicom DM9161E (181b881)
MOTO ENET0, MOTO ENET1, MOTO ENET2
236
Hit any key to stop autoboot:  0
237 238
=>
=> fli
239 240 241 242

Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
  Size: 16 MB in 64 Sectors
  Sector Start Addresses:
243 244 245 246 247 248 249 250 251 252 253 254 255 256 257
    FF000000	  FF040000	FF080000      FF0C0000	    FF100000
    FF140000	  FF180000	FF1C0000      FF200000	    FF240000
    FF280000	  FF2C0000	FF300000      FF340000	    FF380000
    FF3C0000	  FF400000	FF440000      FF480000	    FF4C0000
    FF500000	  FF540000	FF580000      FF5C0000	    FF600000
    FF640000	  FF680000	FF6C0000      FF700000	    FF740000
    FF780000	  FF7C0000	FF800000      FF840000	    FF880000
    FF8C0000	  FF900000	FF940000      FF980000	    FF9C0000
    FFA00000	  FFA40000	FFA80000      FFAC0000	    FFB00000
    FFB40000	  FFB80000	FFBC0000      FFC00000	    FFC40000
    FFC80000	  FFCC0000	FFD00000      FFD40000	    FFD80000
    FFDC0000	  FFE00000	FFE40000      FFE80000	    FFEC0000
    FFF00000	  FFF40000	FFF80000 (RO) FFFC0000 (RO)

=> bdinfo
258
memstart    = 0x00000000
259
memsize	    = 0x10000000
260 261 262 263 264
flashstart  = 0xFF000000
flashsize   = 0x01000000
flashoffset = 0x00000000
sramstart   = 0x00000000
sramsize    = 0x00000000
265 266 267 268 269 270 271 272
immr_base   = 0xE0000000
bootflags   = 0xE4013F80
intfreq	    =	 825 MHz
busfreq	    =	 330 MHz
ethaddr	    = 00:E0:0C:00:00:FD
eth1addr    = 00:E0:0C:00:01:FD
eth2addr    = 00:E0:0C:00:02:FD
IP addr	    = 192.168.1.253
273 274 275
baudrate    = 115200 bps


276 277 278 279 280
=> printenv
bootcmd=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;bootm $loadaddr $ramdiskaddr
nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
bootdelay=10
281 282
baudrate=115200
loads_echo=1
283 284 285 286 287 288 289 290 291 292 293 294 295 296 297
ethaddr=00:E0:0C:00:00:FD
eth1addr=00:E0:0C:00:01:FD
eth2addr=00:E0:0C:00:02:FD
ipaddr=192.168.1.253
serverip=192.168.1.1
rootpath=/nfsroot
gatewayip=192.168.1.1
netmask=255.255.255.0
hostname=unknown
bootfile=your.uImage
loadaddr=200000
netdev=eth0
consoledev=ttyS0
ramdiskaddr=400000
ramdiskfile=your.ramdisk.u-boot
298 299 300
stdin=serial
stdout=serial
stderr=serial
301
ethact=MOTO ENET0
302

303
Environment size: 1020/8188 bytes