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if ARCH_SOCFPGA

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config SPL_LIBCOMMON_SUPPORT
	default y

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config SPL_LIBDISK_SUPPORT
	default y

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config SPL_LIBGENERIC_SUPPORT
	default y

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config SPL_MMC_SUPPORT
	default y if DM_MMC

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config SPL_NAND_SUPPORT
	default y if SPL_NAND_DENALI

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config SPL_SERIAL_SUPPORT
	default y

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config SPL_SPI_FLASH_SUPPORT
	default y if DM_SPI

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config TARGET_SOCFPGA_ARRIA5
	bool
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	select TARGET_SOCFPGA_GEN5
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config TARGET_SOCFPGA_CYCLONE5
	bool
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	select TARGET_SOCFPGA_GEN5

config TARGET_SOCFPGA_GEN5
	bool
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choice
	prompt "Altera SOCFPGA board select"
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	optional
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config TARGET_SOCFPGA_ARRIA5_SOCDK
	bool "Altera SOCFPGA SoCDK (Arria V)"
	select TARGET_SOCFPGA_ARRIA5
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config TARGET_SOCFPGA_CYCLONE5_SOCDK
	bool "Altera SOCFPGA SoCDK (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_DENX_MCVEVK
	bool "DENX MCVEVK (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

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config TARGET_SOCFPGA_EBV_SOCRATES
	bool "EBV SoCrates (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

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config TARGET_SOCFPGA_IS1
	bool "IS1 (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

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config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
	bool "samtec VIN|ING FPGA (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

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config TARGET_SOCFPGA_SR1500
	bool "SR1500 (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

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config TARGET_SOCFPGA_TERASIC_DE0_NANO
	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

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config TARGET_SOCFPGA_TERASIC_SOCKIT
	bool "Terasic SoCkit (Cyclone V)"
	select TARGET_SOCFPGA_CYCLONE5

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endchoice

config SYS_BOARD
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	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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	default "is1" if TARGET_SOCFPGA_IS1
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	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
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	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
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	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
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	default "sr1500" if TARGET_SOCFPGA_SR1500
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	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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config SYS_VENDOR
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	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
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	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
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	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
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config SYS_SOC
	default "socfpga"

config SYS_CONFIG_NAME
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	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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	default "socfpga_is1" if TARGET_SOCFPGA_IS1
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	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
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	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
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	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
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	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
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	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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endif