accessible for core 0. It is part of release.S, within 4KB range after__secondary_start_page. For other cores to use the spin table, the bootingprocess is described below:Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memoryis more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless ofthe physical address of this page, with WIMGE=0b01010. Core 0 also enables bootpage translation for secondary cores to use this page of memory. Then 4KBmemory is copied from __secondary_start_page to the boot page, after flusingcache because this page is mapped as normal DDR. Before copying the reset page,core 0 puts the physical address of the spin table (which is in release.S andrelocated to the top of mapped memory) into a variable __spin_table_addr sothat secondary cores can see it.When secondary cores boot up from 0xffff_f000 page, they only have one defaultTLB. While booting, they set up another TLB in AS=1 space and jump intothe new space. The new TLB covers the physical address of the spin table page,with WIMGE =0b00100. Now secondary cores can keep polling the spin tablewithout stress DDR bus because both the code and the spin table is in cache.For the above to work, DDR has to set the 'M' bit of WIMGE, in order to keepcache coherence.