release.S 10.9 KB
Newer Older
1
/*
2
 * Copyright 2008-2012 Freescale Semiconductor, Inc.
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
 * Kumar Gala <kumar.gala@freescale.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

24
#include <asm-offsets.h>
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
#include <config.h>
#include <mpc85xx.h>
#include <version.h>

#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

/* To boot secondary cpus, we need a place for them to start up.
 * Normally, they start at 0xfffffffc, but that's usually the
 * firmware, and we don't want to have to run the firmware again.
 * Instead, the primary cpu will set the BPTR to point here to
 * this page.  We then set up the core, and head to
 * start_secondary.  Note that this means that the code below
 * must never exceed 1023 instructions (the branch at the end
 * would then be the 1024th).
 */
	.globl	__secondary_start_page
	.align	12
__secondary_start_page:
/* First do some preliminary setup */
	lis	r3, HID0_EMCP@h		/* enable machine check */
51
#ifndef CONFIG_E500MC
52
	ori	r3,r3,HID0_TBEN@l	/* enable Timebase */
53
#endif
54 55 56 57 58
#ifdef CONFIG_PHYS_64BIT
	ori	r3,r3,HID0_ENMAS7@l	/* enable MAS7 updates */
#endif
	mtspr	SPRN_HID0,r3

59
#ifndef CONFIG_E500MC
60
	li	r3,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
61 62 63 64 65 66 67
	mfspr   r0,PVR
	andi.	r0,r0,0xff
	cmpwi	r0,0x50@l	/* if we are rev 5.0 or greater set MBDD */
	blt 1f
	/* Set MBDD bit also */
	ori r3, r3, HID1_MBDD@l
1:
68
	mtspr	SPRN_HID1,r3
69
#endif
70

71 72 73 74 75 76
#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
	mfspr	r3,977
	oris	r3,r3,0x0100
	mtspr	977,r3
#endif

77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
	mfspr	r3,SPRN_SVR
	rlwinm	r3,r3,0,0xff
	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
	cmpw	r3,r4
	beq	1f

#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
	cmpw	r3,r4
	beq	1f
#endif

	/* Not a supported revision affected by erratum */
	b	2f

1:	/* Erratum says set bits 55:60 to 001001 */
	msync
	isync
	mfspr	r3,976
	li	r4,0x48
	rlwimi	r3,r4,0,0x1f8
	mtspr	976,r3
	isync
2:
#endif

104
	/* Enable branch prediction */
105 106
	lis	r3,BUCSR_ENABLE@h
	ori	r3,r3,BUCSR_ENABLE@l
107 108
	mtspr	SPRN_BUCSR,r3

109 110 111 112 113
	/* Ensure TB is 0 */
	li	r3,0
	mttbl	r3
	mttbu	r3

114
	/* Enable/invalidate the I-Cache */
115 116 117 118 119 120 121 122 123 124 125
	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
	mtspr	SPRN_L1CSR1,r2
1:
	mfspr	r3,SPRN_L1CSR1
	and.	r1,r3,r2
	bne	1b

	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
	mtspr	SPRN_L1CSR1,r3
126
	isync
127 128 129 130
2:
	mfspr	r3,SPRN_L1CSR1
	andi.	r1,r3,L1CSR1_ICE@l
	beq	2b
131 132

	/* Enable/invalidate the D-Cache */
133 134 135 136 137 138 139 140 141 142 143
	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
	mtspr	SPRN_L1CSR0,r2
1:
	mfspr	r3,SPRN_L1CSR0
	and.	r1,r3,r2
	bne	1b

	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
	mtspr	SPRN_L1CSR0,r3
144
	isync
145 146 147 148
2:
	mfspr	r3,SPRN_L1CSR0
	andi.	r1,r3,L1CSR0_DCE@l
	beq	2b
149 150 151 152

#define toreset(x) (x - __secondary_start_page + 0xfffff000)

	/* get our PIR to figure out our table entry */
153 154 155
	lis	r3,toreset(__spin_table_addr)@h
	ori	r3,r3,toreset(__spin_table_addr)@l
	lwz	r3,0(r3)
156

157 158 159 160
	/*
	 * r10 has the base address for the entry.
	 * we cannot access it yet before setting up a new TLB
	 */
161
	mfspr	r0,SPRN_PIR
162 163 164 165
#if	defined(CONFIG_E6500)
/*
 * PIR definition for E6500
 * 0-17 Reserved (logic 0s)
166
 * 8-19 CHIP_ID,    2'b00      - SoC 1
167
 *                  all others - reserved
168
 * 20-24 CLUSTER_ID 5'b00000   - CCM 1
169
 *                  all others - reserved
170 171 172 173 174 175 176 177 178 179
 * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
 *                       2'b01 - cluster 2
 *                       2'b10 - cluster 3
 *                       2'b11 - cluster 4
 * 27-28 CORE_ID         2'b00 - core 0
 *                       2'b01 - core 1
 *                       2'b10 - core 2
 *                       2'b11 - core 3
 * 29-31 THREAD_ID       3'b000 - thread 0
 *                       3'b001 - thread 1
180 181 182
 */
	rlwinm  r4,r0,29,25,31
#elif	defined(CONFIG_E500MC)
183 184
	rlwinm	r4,r0,27,27,31
#else
185
	mr	r4,r0
186
#endif
187
	slwi	r8,r4,6	/* spin table is padded to 64 byte */
188 189
	add	r10,r3,r8

190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
#ifdef CONFIG_E6500
	mfspr	r0,SPRN_PIR
	/*
	 * core 0 thread 0: pir reset value 0x00, new pir 0
	 * core 0 thread 1: pir reset value 0x01, new pir 1
	 * core 1 thread 0: pir reset value 0x08, new pir 2
	 * core 1 thread 1: pir reset value 0x09, new pir 3
	 * core 2 thread 0: pir reset value 0x10, new pir 4
	 * core 2 thread 1: pir reset value 0x11, new pir 5
	 * etc.
	 *
	 * Only thread 0 of each core will be running, updating PIR doesn't
	 * need to deal with the thread bits.
	 */
	rlwinm	r4,r0,30,24,30
#endif

	mtspr	SPRN_PIR,r4	/* write to PIR register */

209 210 211 212 213 214 215
#ifdef CONFIG_SYS_CACHE_STASHING
	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
	slwi	r8,r4,1
	addi	r8,r8,32
	mtspr	L1CSR2,r8
#endif

216 217 218 219 220 221 222
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
	/*
	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
	 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
	 */
223
	mfspr   r3,SPRN_SVR
224 225 226 227 228 229 230
	rlwinm	r6,r3,24,~0x800		/* clear E bit */

	lis	r5,SVR_P4080@h
	ori	r5,r5,SVR_P4080@l
	cmpw	r6,r5
	bne	1f

231
	rlwinm  r3,r3,0,0xf0
232 233
	li      r5,0x30
	cmpw    r3,r5
234
	bge     2f
235
1:
236 237 238 239 240 241
#ifdef	CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
	lis	r3,toreset(enable_cpu_a011_workaround)@ha
	lwz	r3,toreset(enable_cpu_a011_workaround)@l(r3)
	cmpwi	r3,0
	beq	2f
#endif
242 243 244
	mfspr	r3,L1CSR2
	oris	r3,r3,(L1CSR2_DCWS)@h
	mtspr	L1CSR2,r3
245
2:
246 247
#endif

248
#ifdef CONFIG_BACKSIDE_L2_CACHE
249
	/* skip L2 setup on P2040/P2040E as they have no L2 */
250 251 252
	mfspr	r3,SPRN_SVR
	rlwinm	r6,r3,24,~0x800		/* clear E bit of SVR */

253 254
	lis	r3,SVR_P2040@h
	ori	r3,r3,SVR_P2040@l
255
	cmpw	r6,r3
256 257
	beq 3f

258 259
	/* Enable/invalidate the L2 cache */
	msync
260 261 262
	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
	mtspr	SPRN_L2CSR0,r2
263 264
1:
	mfspr	r3,SPRN_L2CSR0
265
	and.	r1,r3,r2
266 267
	bne	1b

268 269 270 271 272 273
#ifdef CONFIG_SYS_CACHE_STASHING
	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
	addi	r3,r8,1
	mtspr	SPRN_L2CSR1,r3
#endif

274 275 276 277
	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
	mtspr	SPRN_L2CSR0,r3
	isync
278 279 280 281
2:
	mfspr	r3,SPRN_L2CSR0
	andis.	r1,r3,L2CSR0_L2E@h
	beq	2b
282
#endif
283
3:
284 285 286
	/* setup mapping for the spin table, WIMGE=0b00100 */
	lis	r13,toreset(__spin_table_addr)@h
	ori	r13,r13,toreset(__spin_table_addr)@l
287
	lwz	r13,0(r13)
288 289
	/* mask by 4K */
	rlwinm	r13,r13,0,0,19
290

291 292 293 294 295
	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
	mtspr	SPRN_MAS0,r11
	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
	mtspr	SPRN_MAS1,r11
296 297
	oris	r11,r13,(MAS2_M|MAS2_G)@h
	ori	r11,r13,(MAS2_M|MAS2_G)@l
298
	mtspr	SPRN_MAS2,r11
299 300
	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
301
	mtspr	SPRN_MAS3,r11
302 303
	li	r11,0
	mtspr	SPRN_MAS7,r11
304 305
	tlbwe

306
	/*
307 308
	 * __bootpg_addr has the address of __second_half_boot_page
	 * jump there in AS=1 space with cache enabled
309
	 */
310 311 312 313
	lis	r13,toreset(__bootpg_addr)@h
	ori	r13,r13,toreset(__bootpg_addr)@l
	lwz	r11,0(r13)
	mtspr	SPRN_SRR0,r11
314 315 316 317
	mfmsr	r13
	ori	r12,r13,MSR_IS|MSR_DS@l
	mtspr	SPRN_SRR1,r12
	rfi
318

319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384
	/*
	 * Allocate some space for the SDRAM address of the bootpg.
	 * This variable has to be in the boot page so that it can
	 * be accessed by secondary cores when they come out of reset.
	 */
	.align L1_CACHE_SHIFT
	.globl __bootpg_addr
__bootpg_addr:
	.long	0

	.global __spin_table_addr
__spin_table_addr:
	.long	0

	/*
	 * This variable is set by cpu_init_r() after parsing hwconfig
	 * to enable workaround for erratum NMG_CPU_A011.
	 */
	.align L1_CACHE_SHIFT
	.global enable_cpu_a011_workaround
enable_cpu_a011_workaround:
	.long	1

	/* Fill in the empty space.  The actual reset vector is
	 * the last word of the page */
__secondary_start_code_end:
	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
__secondary_reset_vector:
	b	__secondary_start_page


/* this is a separated page for the spin table and cacheable boot code */
	.align L1_CACHE_SHIFT
	.global __second_half_boot_page
__second_half_boot_page:
#define EPAPR_MAGIC		0x45504150
#define ENTRY_ADDR_UPPER	0
#define ENTRY_ADDR_LOWER	4
#define ENTRY_R3_UPPER		8
#define ENTRY_R3_LOWER		12
#define ENTRY_RESV		16
#define ENTRY_PIR		20
#define ENTRY_SIZE		64
	/*
	 * setup the entry
	 * r10 has the base address of the spin table.
	 * spin table is defined as
	 * struct {
	 *	uint64_t entry_addr;
	 *	uint64_t r3;
	 *	uint32_t rsvd1;
	 *	uint32_t pir;
	 * };
	 * we pad this struct to 64 bytes so each entry is in its own cacheline
	 */
	li	r3,0
	li	r8,1
	mfspr	r4,SPRN_PIR
	stw	r3,ENTRY_ADDR_UPPER(r10)
	stw	r3,ENTRY_R3_UPPER(r10)
	stw	r4,ENTRY_R3_LOWER(r10)
	stw	r3,ENTRY_RESV(r10)
	stw	r4,ENTRY_PIR(r10)
	msync
	stw	r8,ENTRY_ADDR_LOWER(r10)

385
	/* spin waiting for addr */
386
3:	lwz	r4,ENTRY_ADDR_LOWER(r10)
387
	andi.	r11,r4,1
388
	bne	3b
389
	isync
390

391 392 393
	/* setup IVORs to match fixed offsets */
#include "fixed_ivor.S"

394 395
	/* get the upper bits of the addr */
	lwz	r11,ENTRY_ADDR_UPPER(r10)
396 397

	/* setup branch addr */
398
	mtspr	SPRN_SRR0,r4
399 400 401

	/* mark the entry as released */
	li	r8,3
402
	stw	r8,ENTRY_ADDR_LOWER(r10)
403 404

	/* mask by ~64M to setup our tlb we will jump to */
405
	rlwinm	r12,r4,0,0,5
406

407 408 409 410 411 412 413 414 415
	/*
	 * setup r3, r4, r5, r6, r7, r8, r9
	 * r3 contains the value to put in the r3 register at secondary cpu
	 * entry. The high 32-bits are ignored on 32-bit chip implementations.
	 * 64-bit chip implementations however shall load all 64-bits
	 */
#ifdef CONFIG_SYS_PPC64
	ld	r3,ENTRY_R3_UPPER(r10)
#else
416
	lwz	r3,ENTRY_R3_LOWER(r10)
417
#endif
418
	li	r4,0
419
	li	r5,0
420
	li	r6,0
421 422 423
	lis	r7,(64*1024*1024)@h
	li	r8,0
	li	r9,0
424 425

	/* load up the pir */
426
	lwz	r0,ENTRY_PIR(r10)
427 428
	mtspr	SPRN_PIR,r0
	mfspr	r0,SPRN_PIR
429
	stw	r0,ENTRY_PIR(r10)
430

431
	mtspr	IVPR,r12
432 433 434 435 436 437
/*
 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
 * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
 * second mapping that maps addr 1:1 for 64M, and then we jump to
 * addr
 */
438 439 440 441 442
	lis	r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
	mtspr	SPRN_MAS0,r10
	lis	r10,(MAS1_VALID|MAS1_IPROT)@h
	ori	r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
	mtspr	SPRN_MAS1,r10
443
	/* WIMGE = 0b00000 for now */
444 445 446 447 448 449
	mtspr	SPRN_MAS2,r12
	ori	r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
	mtspr	SPRN_MAS3,r12
#ifdef CONFIG_ENABLE_36BIT_PHYS
	mtspr	SPRN_MAS7,r11
#endif
450 451 452 453 454
	tlbwe

/* Now we have another mapping for this page, so we jump to that
 * mapping
 */
455 456
	mtspr	SPRN_SRR1,r13
	rfi
457

458

459
	.align 6
460 461
	.globl __spin_table
__spin_table:
462
	.space CONFIG_MAX_CPUS*ENTRY_SIZE
463 464
__spin_table_end:
	.space 4096 - (__spin_table_end - __spin_table)