• Rajeshwari Shinde's avatar
    spi: exynos: Minimise access to SPI FIFO level · 120af157
    Rajeshwari Shinde authored
    Accessing SPI registers is slow, but access to the FIFO level register
    in particular seems to be extraordinarily expensive (I measure up to
    600ns). Perhaps it is required to synchronise with the SPI byte output
    logic which might run at 1/8th of the 40MHz SPI speed (just a guess).
    Reduce access to this register by filling up and emptying FIFOs
    more completely, rather than just one word each time around the inner
    Since the rxfifo value will now likely be much greater that what we read
    before we fill the txfifo, we only fill the txfifo halfway. This is
    because if the txfifo is empty, but the rxfifo has data in it, then writing
    too much data to the txfifo may overflow the rxfifo as data arrives.
    This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow.
    Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
    Signed-off-by: default avatarRajeshwari S Shinde <rajeshwari.s@samsung.com>
    Reviewed-by: default avatarJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
exynos_spi.c 13.4 KB