• Marek Vasut's avatar
    mmc: dw_mmc: Fix cache alignment issue · 1bf29b3d
    Marek Vasut authored
    The DMA descriptors used by the DW MMC block must be aligned to cacheline
    size, otherwise we are unable to properly flush/inval cache over them and
    we get data corruption.
    
    The reason I chose this approach of expanding the structure is because
    the driver allocates the descriptors in bulk. This approach does waste
    space by inserting slop inbetween the descriptors, but it makes access
    to the descriptors easy as the compiler does know the real size of the
    structure. It also makes cache operations easy, since the size of the
    structure is cache aligned and the structure start address is as well.
    Signed-off-by: default avatarMarek Vasut <marex@denx.de>
    Cc: Chin Liang See <clsee@altera.com>
    Cc: Dinh Nguyen <dinguyen@altera.com>
    Cc: Albert Aribaud <albert.u.boot@aribaud.net>
    Cc: Tom Rini <trini@ti.com>
    Cc: Wolfgang Denk <wd@denx.de>
    Cc: Pavel Machek <pavel@denx.de>
    Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
    Acked-by: default avatarPavel Machek <pavel@denx.de>
    1bf29b3d
dwmmc.h 4.83 KB