• Ye Li's avatar
    MLK-14938-17 pcie: Add support for i.MX8QM/QXP PCIe · 03141c2b
    Ye Li authored
    - one lane pcie gen2 link is okay, the cfg space
      of the rc/ep can be accessed.
      rc cfg base 0x5f00_0000. ep cfg base 0x6000_0000
    - limit to gen2 speed
    - mask the wait of eq3 finish, because it is used
      for gen3.
    - use pcie_ctrla_init_rc() to do the initialization
      of the pciea controller
    - setup the common pcie codes in pcie_imx8x.c, separate
      the different soc speicifed initialization codes into
      their own pcie/board codes, move the macro definitions
      into the new header file imx8_hsio.h.
    - i.MX8QXP only have PCIe Control B. Enable PORT B at default.
      i.MX8QM needs to set CONFIG_IMX_PCIEB to enable PORT B.
    Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
    Signed-off-by: default avatarRichard Zhu <hongxing.zhu@nxp.com>
    Signed-off-by: default avatarShenwei Wang <shenwei.wang@nxp.com>
    Signed-off-by: default avatarYe Li <ye.li@nxp.com>
imx8_hsio.h 8.62 KB