Commit 008e61f5 authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

parents 73c5c399 7711cc0a
......@@ -168,6 +168,25 @@ apply_a57_core_errata:
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
#ifdef CONFIG_ARM_ERRATA_833471
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* FPSCR write flush.
* Note that in some cases where a flush is unnecessary this
could impact performance. */
orr x0, x0, #1 << 38
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
#ifdef CONFIG_ARM_ERRATA_829520
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable Indirect Predictor bit will prevent this erratum
from occurring
* Note that in some cases where a flush is unnecessary this
could impact performance. */
orr x0, x0, #1 << 4
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
#ifdef CONFIG_ARM_ERRATA_833069
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable Enable Invalidates of BTB bit */
......
......@@ -14,6 +14,52 @@
/ {
model = "LS1043A QDS Board";
aliases {
spi0 = &qspi;
spi1 = &dspi0;
};
};
&dspi0 {
bus-num = <0>;
status = "okay";
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <1000000>; /* input clock */
};
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3500000>;
reg = <1>;
};
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3500000>;
reg = <2>;
};
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fl128s@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&i2c0 {
......
......@@ -121,6 +121,12 @@
#define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_ERRATUM_A009942
/* ARM A57 CORE ERRATA */
#define CONFIG_ARM_ERRATA_826974
#define CONFIG_ARM_ERRATA_828024
#define CONFIG_ARM_ERRATA_829520
#define CONFIG_ARM_ERRATA_833471
#elif defined(CONFIG_LS1043A)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_CACHELINE_SIZE 64
......
......@@ -818,6 +818,7 @@ static int dprc_init(void)
goto err_root_open;
}
memset(&cfg, 0, sizeof(struct dprc_cfg));
cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED |
DPRC_CFG_OPT_OBJ_CREATE_ALLOWED |
DPRC_CFG_OPT_ALLOC_ALLOWED;
......@@ -1160,7 +1161,7 @@ int fsl_mc_ldpaa_exit(bd_t *bd)
err = dpbp_exit();
if (err < 0) {
printf("dpni_exit() failed: %d\n", err);
printf("dpbp_exit() failed: %d\n", err);
goto err;
}
......
......@@ -665,5 +665,6 @@ unsigned long get_board_ddr_clk(void);
#endif
#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#endif
......@@ -523,5 +523,6 @@
#endif
#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#endif
......@@ -15,9 +15,6 @@
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
/* Errata fixes */
#define CONFIG_ARM_ERRATA_828024
#define CONFIG_ARM_ERRATA_826974
#include <asm/arch/ls2080a_stream_id.h>
#include <asm/arch/config.h>
......
......@@ -346,7 +346,7 @@ unsigned long get_board_ddr_clk(void);
"initrd_high=0xffffffffffffffff\0" \
"kernel_start=0x581100000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x28000000\0"
"kernel_size=0x2800000\0"
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_FSL_MEMAC
......
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