Commit 028dbb8d authored by Ruchika Gupta's avatar Ruchika Gupta Committed by York Sun

fsl_sec : Change accessor function to take care of endianness

SEC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of SEC IP.

So update acessor functions with common SEC acessor functions to take care
both type of endianness.
Signed-off-by: default avatarRuchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
parent 48ef0d2a
...@@ -544,6 +544,12 @@ The following options need to be configured: ...@@ -544,6 +544,12 @@ The following options need to be configured:
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Number of controllers used for other than main memory. Number of controllers used for other than main memory.
CONFIG_SYS_FSL_SEC_BE
Defines the SEC controller register space as Big Endian
CONFIG_SYS_FSL_SEC_LE
Defines the SEC controller register space as Little Endian
- Intel Monahans options: - Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
......
...@@ -803,7 +803,7 @@ int cpu_init_r(void) ...@@ -803,7 +803,7 @@ int cpu_init_r(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
#define MCFGR_AXIPIPE 0x000000f0 #define MCFGR_AXIPIPE 0x000000f0
if (IS_SVR_REV(svr, 1, 0)) if (IS_SVR_REV(svr, 1, 0))
clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE); sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
#endif #endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
......
...@@ -714,7 +714,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) ...@@ -714,7 +714,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ccsr_sec_t __iomem *sec; ccsr_sec_t __iomem *sec;
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms)); fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
} }
#endif #endif
......
...@@ -66,12 +66,12 @@ static void setup_sec_liodn_base(void) ...@@ -66,12 +66,12 @@ static void setup_sec_liodn_base(void)
return; return;
/* QILCR[QSLOM] */ /* QILCR[QSLOM] */
out_be32(&sec->qilcr_ms, 0x3ff<<16); sec_out32(&sec->qilcr_ms, 0x3ff<<16);
base = (liodn_bases[FSL_HW_PORTAL_SEC].id[0] << 16) | base = (liodn_bases[FSL_HW_PORTAL_SEC].id[0] << 16) |
liodn_bases[FSL_HW_PORTAL_SEC].id[1]; liodn_bases[FSL_HW_PORTAL_SEC].id[1];
out_be32(&sec->qilcr_ls, base); sec_out32(&sec->qilcr_ls, base);
} }
#ifdef CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN
......
...@@ -287,8 +287,8 @@ static u8 caam_get_era(void) ...@@ -287,8 +287,8 @@ static u8 caam_get_era(void)
}; };
ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
u32 secvid_ms = in_be32(&sec->secvid_ms); u32 secvid_ms = sec_in32(&sec->secvid_ms);
u32 ccbvid = in_be32(&sec->ccbvid); u32 ccbvid = sec_in32(&sec->ccbvid);
u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >> u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
SEC_SECVID_MS_IPID_SHIFT; SEC_SECVID_MS_IPID_SHIFT;
u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >> u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >>
......
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
/* IP endianness */ /* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_SEC_BE
/* Number of TLB CAM entries we have on FSL Book-E chips */ /* Number of TLB CAM entries we have on FSL Book-E chips */
#if defined(CONFIG_E500MC) #if defined(CONFIG_E500MC)
......
...@@ -11,6 +11,22 @@ ...@@ -11,6 +11,22 @@
#include <common.h> #include <common.h>
#include <asm/io.h> #include <asm/io.h>
#ifdef CONFIG_SYS_FSL_SEC_LE
#define sec_in32(a) in_le32(a)
#define sec_out32(a, v) out_le32(a, v)
#define sec_in16(a) in_le16(a)
#define sec_clrbits32 clrbits_le32
#define sec_setbits32 setbits_le32
#elif defined(CONFIG_SYS_FSL_SEC_BE)
#define sec_in32(a) in_be32(a)
#define sec_out32(a, v) out_be32(a, v)
#define sec_in16(a) in_be16(a)
#define sec_clrbits32 clrbits_be32
#define sec_setbits32 setbits_be32
#else
#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
#endif
/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
typedef struct ccsr_sec { typedef struct ccsr_sec {
......
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