Commit 02ebe6f7 authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

parents 7ae8350f 32df39c7
......@@ -4422,6 +4422,9 @@ to save the current settings.
If defined, specified the chip address of the EEPROM device.
The default address is zero.
- CONFIG_SYS_I2C_EEPROM_BUS:
If defined, specified the i2c bus of the EEPROM device.
- CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
If defined, the number of bits used to address bytes in a
single page in the EEPROM device. A 64 byte page, for example
......
......@@ -465,6 +465,10 @@ config TARGET_WANDBOARD
bool "Support wandboard"
select CPU_V7
config TARGET_WARP
bool "Support WaRP"
select CPU_V7
config TARGET_TITANIUM
bool "Support titanium"
select CPU_V7
......@@ -842,6 +846,7 @@ source "board/ttcontrol/vision2/Kconfig"
source "board/udoo/Kconfig"
source "board/vpac270/Kconfig"
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
source "board/woodburn/Kconfig"
source "board/xaeniax/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
......
......@@ -8,3 +8,7 @@
obj-y += generic.o
obj-y += timer.o
obj-y += devices.o
ifndef CONFIG_SPL_BUILD
obj-y += relocate.o
endif
/*
* relocate - i.MX31-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
/*
* The i.MX31 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM, so let's avoid relocating the vectors.
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
bx lr
ENDPROC(relocate_vectors)
......@@ -10,3 +10,7 @@
obj-y += generic.o
obj-y += timer.o
obj-y += mx35_sdram.o
ifndef CONFIG_SPL_BUILD
obj-y += relocate.o
endif
/*
* relocate - i.MX35-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
/*
* The i.MX35 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM, so let's avoid relocating the vectors.
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
bx lr
ENDPROC(relocate_vectors)
......@@ -230,6 +230,11 @@ static void imx_set_wdog_powerdown(bool enable)
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
#ifdef CONFIG_MX6SX
struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
writew(enable, &wdog3->wmcr);
#endif
/* Write to the PDE (Power Down Enable) bit */
writew(enable, &wdog1->wmcr);
writew(enable, &wdog2->wmcr);
......@@ -255,6 +260,23 @@ static void clear_mmdc_ch_mask(void)
writel(0, &mxc_ccm->ccdr);
}
static void init_bandgap(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
/*
* Ensure the bandgap has stabilized.
*/
while (!(readl(&anatop->ana_misc0) & 0x80))
;
/*
* For best noise performance of the analog blocks using the
* outputs of the bandgap, the reftop_selfbiasoff bit should
* be set.
*/
writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
}
#ifdef CONFIG_MX6SL
static void set_preclk_from_osc(void)
{
......@@ -274,6 +296,13 @@ int arch_cpu_init(void)
/* Need to clear MMDC_CHx_MASK to make warm reset work. */
clear_mmdc_ch_mask();
/*
* Disable self-bias circuit in the analog bandap.
* The self-bias circuit is used by the bandgap during startup.
* This bit should be set after the bandgap has initialized.
*/
init_bandgap();
/*
* When low freq boot is enabled, ROM will not set AHB
* freq, so we need to ensure AHB freq is 132MHz in such
......
......@@ -24,6 +24,7 @@ obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
quiet_cmd_cpp_cfg = CFGS $@
cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $<
......
/*
* Copyright 2008-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Command for encapsulating DEK blob
*/
#include <common.h>
#include <command.h>
#include <environment.h>
#include <malloc.h>
#include <asm/byteorder.h>
#include <linux/compiler.h>
#include <fsl_sec.h>
#include <asm/arch/clock.h>
DECLARE_GLOBAL_DATA_PTR;
/**
* blob_dek() - Encapsulate the DEK as a blob using CAM's Key
* @src: - Address of data to be encapsulated
* @dst: - Desination address of encapsulated data
* @len: - Size of data to be encapsulated
*
* Returns zero on success,and negative on error.
*/
static int blob_encap_dek(const u8 *src, u8 *dst, u32 len)
{
int ret = 0;
u32 jr_size = 4;
u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c);
if (out_jr_size != jr_size) {
hab_caam_clock_enable(1);
sec_init();
}
if (!((len == 128) | (len == 192) | (len == 256))) {
debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
return -1;
}
len /= 8;
ret = blob_dek(src, dst, len);
return ret;
}
/**
* do_dek_blob() - Handle the "dek_blob" command-line command
* @cmdtp: Command data struct pointer
* @flag: Command flag
* @argc: Command-line argument count
* @argv: Array of command-line arguments
*
* Returns zero on success, CMD_RET_USAGE in case of misuse and negative
* on error.
*/
static int do_dek_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
uint32_t src_addr, dst_addr, len;
uint8_t *src_ptr, *dst_ptr;
int ret = 0;
if (argc != 4)
return CMD_RET_USAGE;
src_addr = simple_strtoul(argv[1], NULL, 16);
dst_addr = simple_strtoul(argv[2], NULL, 16);
len = simple_strtoul(argv[3], NULL, 10);
src_ptr = map_sysmem(src_addr, len/8);
dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len/8));
ret = blob_encap_dek(src_ptr, dst_ptr, len);
return ret;
}
/***************************************************/
static char dek_blob_help_text[] =
"src dst len - Encapsulate and create blob of data\n"
" $len bits long at address $src and\n"
" store the result at address $dst.\n";
U_BOOT_CMD(
dek_blob, 4, 1, do_dek_blob,
"Data Encryption Key blob encapsulation",
dek_blob_help_text
);
......@@ -24,13 +24,16 @@
#include <fsl_esdhc.h>
#endif
char *get_reset_cause(void)
static u32 reset_cause = -1;
static char *get_reset_cause(void)
{
u32 cause;
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
cause = readl(&src_regs->srsr);
writel(cause, &src_regs->srsr);
reset_cause = cause;
switch (cause) {
case 0x00001:
......@@ -53,6 +56,11 @@ char *get_reset_cause(void)
}
}
u32 get_imx_reset_cause(void)
{
return reset_cause;
}
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
#if defined(CONFIG_MX53)
#define MEMCTL_BASE ESDCTL_BASE_ADDR
......
......@@ -176,3 +176,20 @@ ulong get_tbclk(void)
{
return gpt_get_clk();
}
/*
* This function is intended for SHORT delays only.
* It will overflow at around 10 seconds @ 400MHz,
* or 20 seconds @ 200MHz.
*/
unsigned long usec2ticks(unsigned long usec)
{
ulong ticks;
if (usec < 1000)
ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
else
ticks = ((usec / 10) * (get_tbclk() / 100000));
return ticks;
}
......@@ -17,3 +17,5 @@
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
u32 get_imx_reset_cause(void);
......@@ -24,6 +24,5 @@ void set_chipselect_size(int const);
int fecmxc_initialize(bd_t *bis);
u32 get_ahb_clk(void);
u32 get_periph_clk(void);
char *get_reset_cause(void);
#endif
......@@ -1063,4 +1063,6 @@ struct mxc_ccm_reg {
#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
......@@ -215,6 +215,10 @@
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
#define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR
#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000)
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
......
......@@ -31,7 +31,12 @@ enum {
MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT4__USDHC2_DAT4 = IOMUX_PAD(0X0574, 0X026C, 0, 0X0000, 0, 0),
MX6_PAD_SD2_DAT5__USDHC2_DAT5 = IOMUX_PAD(0X0578, 0X0270, 0, 0X0000, 0, 0),
MX6_PAD_SD2_DAT6__USDHC2_DAT6 = IOMUX_PAD(0X057C, 0X0274, 0, 0X0000, 0, 0),
MX6_PAD_SD2_DAT7__USDHC2_DAT7 = IOMUX_PAD(0X0580, 0X0278, 0, 0X0000, 0, 0),
MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
MX6_PAD_SD2_RST__USDHC2_RST = IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0),
......@@ -58,5 +63,10 @@ enum {
MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0),
MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0),
MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
MX6_PAD_I2C1_SDA__GPIO_3_13 = IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0),
MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
MX6_PAD_I2C1_SCL__GPIO_3_12 = IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
......@@ -1018,5 +1018,6 @@ int misc_init_r(void)
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
setenv_hex("reset_cause", get_imx_reset_cause());
return 0;
}
......@@ -5,9 +5,47 @@
*/
#include <common.h>
#include <errno.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
int pfuze_mode_init(struct pmic *p, u32 mode)
{
unsigned char offset, i, switch_num;
u32 id, ret;
pmic_reg_read(p, PFUZE100_DEVICEID, &id);
id = id & 0xf;
if (id == 0) {
switch_num = 6;
offset = PFUZE100_SW1CMODE;
} else if (id == 1) {
switch_num = 4;
offset = PFUZE100_SW2MODE;
} else {
printf("Not supported, id=%d\n", id);
return -EINVAL;
}
ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
if (ret < 0) {
printf("Set SW1AB mode error!\n");
return ret;
}
for (i = 0; i < switch_num - 1; i++) {
ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
if (ret < 0) {
printf("Set switch 0x%x mode error!\n",
offset + i * SWITCH_SIZE);
return ret;
}
}
return ret;
}
struct pmic *pfuze_common_init(unsigned char i2cbus)
{
struct pmic *p;
......
......@@ -8,5 +8,6 @@
#define __PFUZE_BOARD_HELPER__
struct pmic *pfuze_common_init(unsigned char i2cbus);
int pfuze_mode_init(struct pmic *p, u32 mode);
#endif
......@@ -146,8 +146,8 @@ int board_late_init(void)
if (!p)
return -ENODEV;
/* Turn on Ethernet PHY supply */
pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
/* Turn on Ethernet PHY and LCD supplies */
pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE | ONOFFA);
return 0;
}
......
......@@ -366,22 +366,6 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
u32 cpurev;
cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
(cpurev & 0xFF000) >> 12,
(cpurev & 0x000F0) >> 4,
(cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
/*
* Do not overwrite the console
* Use always serial for U-Boot console
......
......@@ -29,6 +29,7 @@
#include <asm/arch/crm_regs.h>
#include <pca953x.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
DECLARE_GLOBAL_DATA_PTR;
......@@ -494,11 +495,16 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
int power_init_board(void)
{
struct pmic *p;
unsigned int ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
ret = pfuze_mode_init(p, APS_PFM);
if (ret < 0)
return ret;
return 0;
}
......
......@@ -631,12 +631,16 @@ int board_init(void)
int power_init_board(void)
{
struct pmic *p;
unsigned int reg;
unsigned int reg, ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
ret = pfuze_mode_init(p, APS_PFM);
if (ret < 0)
return ret;
/* Increase VGEN3 from 2.5 to 2.8V */
pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
reg &= ~LDO_VOL_MASK;
......
......@@ -13,13 +13,18 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/spi.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <mmc.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
#include <usb.h>
#include <usb/ehci-fsl.h>
......@@ -40,6 +45,16 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
PAD_CTL_SRE_FAST)
#define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
int dram_init(void)
......@@ -221,6 +236,34 @@ int board_mmc_init(bd_t *bis)
return 0;
}
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
struct i2c_pads_info i2c_pad_info1 = {
.sda = {
.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
.gp = IMX_GPIO_NR(3, 13),
},
.scl = {
.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
.gp = IMX_GPIO_NR(3, 12),
},
};
int power_init_board(void)
{
struct pmic *p;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
return pfuze_mode_init(p, APS_PFM);
}
#endif
#ifdef CONFIG_FEC_MXC
int board_eth_init(bd_t *bis)
{
......@@ -247,7 +290,7 @@ static int setup_fec(void)
static iomux_v3_cfg_t const usb_otg_pads[] = {
/* OTG1 */
MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
/* OTG2 */
MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
};
......@@ -297,6 +340,10 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
......
......@@ -199,12 +199,16 @@ static struct i2c_pads_info i2c_pad_info1 = {
int power_init_board(void)
{
struct pmic *p;
unsigned int reg;
unsigned int reg, ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
ret = pfuze_mode_init(p, APS_PFM);
if (ret < 0)
return ret;
/* Enable power of VGEN5 3V3, needed for SD3 */
pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
reg &= ~LDO_VOL_MASK;
......
......@@ -326,21 +326,25 @@ static void setup_display(void)
reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
writel(reg, &ccm->analog_pll_video);
/* select video pll for ldb_di0_clk */
reg = readl(&ccm->cs2cdr);
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
writel(reg, &ccm->cs2cdr);
/* gate ipu1_di0_clk */
reg = readl(&ccm->CCGR3);
reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
writel(reg, &ccm->CCGR3);
/* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */
reg = readl(&ccm->cscmr2);
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
writel(reg, &ccm->cscmr2);
/* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */
/* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
reg = readl(&ccm->chsccdr);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
(6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
(0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &ccm->chsccdr);
/* enable ipu1_di0_clk */
reg = readl(&ccm->CCGR3);
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
writel(reg, &ccm->CCGR3);
}
#endif /* CONFIG_VIDEO_IPUV3 */
......
if TARGET_WARP
config SYS_BOARD
default "warp"
config SYS_SOC
default "mx6"
config SYS_CONFIG_NAME
default "warp"
endif
WaRP BOARD
M: Otavio Salvador <otavio@ossystems.com.br>
S: Maintained
F: board/warp/
F: include/configs/warp.h
F: configs/warp_defconfig
# Copyright (C) 2014 O.S. Systems Software LTDA.
# Copyright (C) 2014 Kynetics LLC.
# Copyright (C) 2014 Revolution Robotics, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := warp.o
/*
* Copyright (C) 2014, 2015 O.S. Systems Software LTDA.
* Copyright (C) 2014 Kynetics LLC.
* Copyright (C) 2014 Revolution Robotics, Inc.
*
* Author: Otavio Salvador <otavio@ossystems.com.br>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <watchdog.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS | \
PAD_CTL_LVE)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS | \