Commit 03a14104 authored by Wolfgang Denk's avatar Wolfgang Denk

Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

parents 3cb7a480 c2e49f70
......@@ -32,6 +32,8 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com>
mecp5200 MPC5200
pf5200 MPC5200
vme8349 MPC8349
CPCI750 PPC750FX/GX
Yuli Barcohen <yuli@arabellasw.com>
......
......@@ -364,6 +364,7 @@ LIST_83xx=" \
sbc8349 \
SIMPC8313_LP \
TQM834x \
vme8349 \
"
......
......@@ -2387,6 +2387,8 @@ SIMPC8313_SP_config: unconfig
TQM834x_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
vme8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx vme8349 esd
#########################################################################
## MPC85xx Systems
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (c) 2009 esd gmbh hannover germany.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o caddy.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
* Copyright (c) 2009 esd gmbh.
*
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <pci.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include "caddy.h"
static struct caddy_interface *caddy_interface;
void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
{
struct caddy_answer *answer;
uint32_t ptr;
answer = &caddy_interface->answer[caddy_interface->answer_in];
memset((void *)answer, 0, sizeof(struct caddy_answer));
answer->answer = cmd->cmd;
answer->issue = cmd->issue;
answer->status = status;
memcpy(answer->par, result, 5 * sizeof(result[0]));
ptr = caddy_interface->answer_in + 1;
ptr = ptr & (ANSWER_SIZE - 1);
if (ptr != caddy_interface->answer_out)
caddy_interface->answer_in = ptr;
}
int do_caddy(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned long base_addr;
uint32_t ptr;
struct caddy_cmd *caddy_cmd;
uint32_t result[5];
uint16_t data16;
uint8_t data8;
uint32_t status;
pci_dev_t dev;
void *pci_ptr;
if (argc < 2) {
puts("Missing parameter\n");
return 1;
}
base_addr = simple_strtoul(argv[1], NULL, 16);
caddy_interface = (struct caddy_interface *) base_addr;
memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
while (ctrlc() == 0) {
if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
memset(result, 0, 5 * sizeof(result[0]));
status = 0;
caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
(caddy_cmd->addr & 0x001fffff);
switch (caddy_cmd->cmd) {
case CADDY_CMD_IO_READ_8:
result[0] = in_8(pci_ptr);
break;
case CADDY_CMD_IO_READ_16:
result[0] = in_be16(pci_ptr);
break;
case CADDY_CMD_IO_READ_32:
result[0] = in_be32(pci_ptr);
break;
case CADDY_CMD_IO_WRITE_8:
data8 = caddy_cmd->par[0] & 0x000000ff;
out_8(pci_ptr, data8);
break;
case CADDY_CMD_IO_WRITE_16:
data16 = caddy_cmd->par[0] & 0x0000ffff;
out_be16(pci_ptr, data16);
break;
case CADDY_CMD_IO_WRITE_32:
out_be32(pci_ptr, caddy_cmd->par[0]);
break;
case CADDY_CMD_CONFIG_READ_8:
dev = PCI_BDF(caddy_cmd->par[0],
caddy_cmd->par[1],
caddy_cmd->par[2]);
status = pci_read_config_byte(dev,
caddy_cmd->addr,
&data8);
result[0] = data8;
break;
case CADDY_CMD_CONFIG_READ_16:
dev = PCI_BDF(caddy_cmd->par[0],
caddy_cmd->par[1],
caddy_cmd->par[2]);
status = pci_read_config_word(dev,
caddy_cmd->addr,
&data16);
result[0] = data16;
break;
case CADDY_CMD_CONFIG_READ_32:
dev = PCI_BDF(caddy_cmd->par[0],
caddy_cmd->par[1],
caddy_cmd->par[2]);
status = pci_read_config_dword(dev,
caddy_cmd->addr,
&result[0]);
break;
case CADDY_CMD_CONFIG_WRITE_8:
dev = PCI_BDF(caddy_cmd->par[0],
caddy_cmd->par[1],
caddy_cmd->par[2]);
data8 = caddy_cmd->par[3] & 0x000000ff;
status = pci_write_config_byte(dev,
caddy_cmd->addr,
data8);
break;
case CADDY_CMD_CONFIG_WRITE_16:
dev = PCI_BDF(caddy_cmd->par[0],
caddy_cmd->par[1],
caddy_cmd->par[2]);
data16 = caddy_cmd->par[3] & 0x0000ffff;
status = pci_write_config_word(dev,
caddy_cmd->addr,
data16);
break;
case CADDY_CMD_CONFIG_WRITE_32:
dev = PCI_BDF(caddy_cmd->par[0],
caddy_cmd->par[1],
caddy_cmd->par[2]);
status = pci_write_config_dword(dev,
caddy_cmd->addr,
caddy_cmd->par[3]);
break;
default:
status = 0xffffffff;
break;
}
generate_answer(caddy_cmd, status, &result[0]);
ptr = caddy_interface->cmd_out + 1;
ptr = ptr & (CMD_SIZE - 1);
caddy_interface->cmd_out = ptr;
}
caddy_interface->heartbeat++;
}
return 0;
}
U_BOOT_CMD(
caddy, 2, 0, do_caddy,
"Start Caddy server.",
"Start Caddy server with Data structure a given addr\n"
);
/*
* caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
* Copyright (c) 2009 esd gmbh.
*
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __CADDY_H__
#define __CADDY_H__
#define CMD_SIZE 1024
#define ANSWER_SIZE 1024
#define CADDY_MAGIC "esd vme8349 V1.0"
enum caddy_cmds {
CADDY_CMD_IO_READ_8,
CADDY_CMD_IO_READ_16,
CADDY_CMD_IO_READ_32,
CADDY_CMD_IO_WRITE_8,
CADDY_CMD_IO_WRITE_16,
CADDY_CMD_IO_WRITE_32,
CADDY_CMD_CONFIG_READ_8,
CADDY_CMD_CONFIG_READ_16,
CADDY_CMD_CONFIG_READ_32,
CADDY_CMD_CONFIG_WRITE_8,
CADDY_CMD_CONFIG_WRITE_16,
CADDY_CMD_CONFIG_WRITE_32,
};
struct caddy_cmd {
uint32_t cmd;
uint32_t issue;
uint32_t addr;
uint32_t par[5];
};
struct caddy_answer {
uint32_t answer;
uint32_t issue;
uint32_t status;
uint32_t par[5];
};
struct caddy_interface {
uint8_t magic[16];
uint32_t cmd_in;
uint32_t cmd_out;
uint32_t heartbeat;
uint32_t reserved1;
struct caddy_cmd cmd[CMD_SIZE];
uint32_t answer_in;
uint32_t answer_out;
uint32_t reserved2;
uint32_t reserved3;
struct caddy_answer answer[CMD_SIZE];
};
#endif /* of __CADDY_H__ */
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# VME8349E
#
TEXT_BASE = 0xFFF00000
/*
* pci.c -- esd VME8349 PCI board support.
* Copyright (c) 2006 Wind River Systems, Inc.
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Based on MPC8349 PCI support but w/o PIB related code.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
#include <asm/fsl_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
size: CONFIG_SYS_PCI1_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CONFIG_SYS_PCI1_IO_BASE,
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
size: CONFIG_SYS_PCI1_IO_SIZE,
flags: PCI_REGION_IO
},
{
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
size: CONFIG_SYS_PCI1_MMIO_SIZE,
flags: PCI_REGION_MEM
},
};
/*
* pci_init_board()
*
* NOTICE: PCI2 is not supported. There is only one
* physical PCI slot on the board.
*
*/
void
pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci1_regions };
u8 reg8;
int monarch = 0;
i2c_set_bus_num(1);
/* Read the PCI_M66EN jumper setting */
if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, 1) == 0) ||
(i2c_read(0x38 , 0, 0, &reg8, 1) == 0)) {
if (reg8 & 0x40) {
clk->occr = 0xff000000; /* 66 MHz PCI */
printf("PCI: 66MHz\n");
} else {
clk->occr = 0xffff0003; /* 33 MHz PCI */
printf("PCI: 33MHz\n");
}
if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
monarch = 1;
} else {
clk->occr = 0xffff0003; /* 33 MHz PCI */
printf("PCI: 33MHz (I2C read failed)\n");
}
udelay(2000);
/*
* Assert/deassert PCI reset
*/
setbits_be32(&immr->gpio[0].dat, 0x00800000);
setbits_be32(&immr->gpio[0].dir, 0x00800000);
setbits_be32(&immr->gpio[1].dir, 0x08800000);
udelay(200);
setbits_be32(&immr->gpio[1].dat, 0x08000000);
udelay(200);
setbits_be32(&immr->gpio[1].dat, 0x08800000);
udelay(600000);
clrbits_be32(&immr->gpio[1].dat, 0x00100000);
/* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
udelay(2000);
if (monarch == 0)
mpc83xx_pci_init(1, reg, 0);
}
/*
* vme8349.c -- esd VME8349 board support
*
* Copyright (c) 2008-2009 esd gmbh.
*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <asm/io.h>
#include <asm/mmu.h>
void ddr_enable_ecc(unsigned int dram_size);
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
msize = CONFIG_SYS_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1);
ddr_size = ddr_size>>1, ddr_size_log2++) {
if (ddr_size & 1)
return -1;
}
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE == 512)
im->ddr.csbnds[0].csbnds = 0x0000001f;
#else
#warning Currently any DDR size other than 512MiB is not supported
#endif
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG | 0x00330000;
/* currently we use only one CS, so disable the other banks */
im->ddr.csbnds[1].csbnds = 0x00000000;
im->ddr.csbnds[2].csbnds = 0x00000000;
im->ddr.csbnds[3].csbnds = 0x00000000;
im->ddr.cs_config[1] = 0;
im->ddr.cs_config[2] = 0;
im->ddr.cs_config[3] = 0;
im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
sync();
udelay(200);
/* enable DDR controller */
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
return msize;
}
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
/* Now check memory size (after ECC is initialized) */
msize = get_ram_size(0, msize);
/* return total bus SDRAM size(bytes) -- DDR */
return msize * 1024 * 1024;
}
int checkboard(void)
{
puts("Board: esd VME8349\n");
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif
......@@ -24,4 +24,4 @@
# SBC8349E
#
TEXT_BASE = 0xFFF00000
TEXT_BASE = 0xFF800000
......@@ -38,8 +38,8 @@ COBJS-y += spd_sdram.o
COBJS-y += ecc.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_FSL_SERDES) += serdes.o
COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o
COBJS-$(CONFIG_83XX_GENERIC_PCIE) += pcie.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-$(CONFIG_PCIE) += pcie.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS := $(COBJS-y)
......
......@@ -21,15 +21,22 @@ Flash Details:
The flash type is intel 28F640Jx (4096x16) [one device]. Base address
is 0xFF80_0000 which is also where the Hardware Reset Configuration
Word (HRCW) is stored. Caution should be used to not overwrite the
HRCW, or "CF RCW" with a Wind River ICE will be required to restore
the HRCW and allow the board to enter background mode for further
steps in the flash process.
Word (HRCW) is stored. Caution should be used to not reset the
board without having a valid HRCW in place (i.e. erased flash) as
then a Wind River ICE will be required to restore the HRCW and flash
image.
Restoring a corrupted or missing flash image:
=============================================
Note that U-boot versions up to and including 2009.06 had essentially
two copies of u-boot in flash; one at the very beginning, which set
the HRCW, and one at the very end, which was the image that was run.
As of this point in time, the two have been combined into just one
at the beginning of flash, which provides both the HRCW, and the image
that is executed. This frees up the remainder of flash for other uses.
Use of the u-boot command "fli" will indicate what parts are in use.
Details for storing U-boot to flash using a Wind River ICE can be found
on page 19 of the board manual (request ERG-00328-001). The following
is a summary of that information:
......@@ -39,9 +46,9 @@ is a summary of that information:
- Select the appropriate flash type (listed above)
- Prepare a u-boot image by using the Wind River Convert utility;
by using "Convert and Add file" on the ELF file from your build.
Convert from FFF0_0000 to FFFF_FFFF (or to FFF3_FFFF if you are
trying to preserve your old environment settings).
- Set the start address of the erase/flash process to FFF0_0000
Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are
trying to preserve your old environment settings and user flash).
- Set the start address of the erase/flash process to FF80_0000
- Set the target RAM required to 64kB.
- Select sectors for erasing (see note on enviroment below)
- Select Erase and Reprogram.
......@@ -59,7 +66,7 @@ beginning with "SCGA TSEC1" and "SCGA TSEC2". This allows you to
use all the remaining register file content.
If you wish to preserve your prior U-Boot environment settings,
then convert (and erase to) 0xFFF3FFFF instead of 0xFFFFFFFF.
then convert (and erase to) 0xFF83FFFF instead of 0xFFFFFFFF.
The size for converting (and erasing) must be at least as large
as u-boot.bin.
......@@ -73,10 +80,13 @@ has been copied to the TFTP server, the commands are:
tftp 200000 u-boot.bin
protect off all
erase fff00000 fff3ffff
cp.b 200000 fff00000 3ffff
erase ff800000 ff83ffff
cp.b 200000 ff800000 40000
protect on all
You may wish to do a "md ff800000 20" operation as a prefix and postfix
to the above steps to inspect/compare the HRCW before/after as an extra
safety check before resetting the board upon completion of the reflash.
PCI:
====
......
......@@ -403,7 +403,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
PCI_DEV(dev));
break;
#endif
#ifdef CONFIG_MPC834x
#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents
......
......@@ -36,7 +36,6 @@
#define CONFIG_MPC8313ERDB 1
#define CONFIG_PCI
#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_MISC_INIT_R
......