Commit 03f2ecc2 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Tom Rini

powerpc: remove MOUSSE board support

Enough time has passed since this board was moved to Orphan. Remove.

 - Remove board/mousse/*
 - Remove include/configs/MOUSSE.h
 - Clean-up defined(CONFIG_MOUSSE)
 - Move the entry from boards.cfg to doc/README.scrapyard
Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
parent 8b043e6d
......@@ -120,10 +120,6 @@ N: Dan A. Dickey
E: ddickey@charter.net
D: FADS Support
N: James F. Dougherty
E: jfd@GigabitNetworks.COM
D: Port to the MOUSSE board
N: Mike Dunn
E: mikedunn@newsguy.com
D: Palmtreo680 board, docg4 nand flash driver
......
......@@ -46,8 +46,6 @@
void
cpu_init_f (void)
{
/* MOUSSE board is initialized in asm */
#if !defined(CONFIG_MOUSSE)
register unsigned long val;
CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
......@@ -302,98 +300,12 @@ cpu_init_f (void)
CONFIG_READ_WORD(MCCR1, val);
CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
__asm__ __volatile__("eieio");
#endif /* !CONFIG_MOUSSE */
}
#ifdef CONFIG_MOUSSE
#ifdef INCLUDE_MPC107_REPORT
struct MPC107_s {
unsigned int iobase;
char desc[120];
} MPC107Regs[] = {
{ BMC_BASE + 0x00, "MPC107 Vendor/Device ID" },
{ BMC_BASE + 0x04, "MPC107 PCI Command/Status Register" },
{ BMC_BASE + 0x08, "MPC107 Revision" },
{ BMC_BASE + 0x0C, "MPC107 Cache Line Size" },
{ BMC_BASE + 0x10, "MPC107 LMBAR" },
{ BMC_BASE + 0x14, "MPC824x PCSR" },
{ BMC_BASE + 0xA8, "MPC824x PICR1" },
{ BMC_BASE + 0xAC, "MPC824x PICR2" },
{ BMC_BASE + 0x46, "MPC824x PACR" },
{ BMC_BASE + 0x310, "MPC824x ITWR" },
{ BMC_BASE + 0x300, "MPC824x OMBAR" },
{ BMC_BASE + 0x308, "MPC824x OTWR" },
{ BMC_BASE + 0x14, "MPC107 Peripheral Control and Status Register" },
{ BMC_BASE + 0x78, "MPC107 EUMBAR" },
{ BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status" },
{ BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status" },
{ BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" },
{ BMC_BASE + 0xE0, "MPC107 AMBOR Register" },
{ BMC_BASE + 0xF0, "MPC107 MCCR1 Register" },
{ BMC_BASE + 0xF4, "MPC107 MCCR2 Register" },
{ BMC_BASE + 0xF8, "MPC107 MCCR3 Register" },
{ BMC_BASE + 0xFC, "MPC107 MCCR4 Register" },
};
#define N_MPC107_Regs (sizeof(MPC107Regs)/sizeof(MPC107Regs[0]))
#endif /* INCLUDE_MPC107_REPORT */
#endif /* CONFIG_MOUSSE */
/*
* initialize higher level parts of CPU like time base and timers
*/
int cpu_init_r (void)
{
#ifdef CONFIG_MOUSSE
#ifdef INCLUDE_MPC107_REPORT
unsigned int tmp = 0, i;
#endif
/*
* Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg).
* This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can
* be accessed.
*/
#ifdef CONFIG_MPC8240 /* only on MPC8240 */
mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL);
/* MOT/SPS: Issue #10002, PCI (FD Alias enable) */
mpc824x_mpc107_setreg (AMBOR, 0x000000C0);
#endif
#ifdef INCLUDE_MPC107_REPORT
/* Check MPC824x PCI Device and Vendor ID */
while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) {
printf (" MPC107: offset=0x%x, val = 0x%x\n",
BMC_BASE,
tmp);
}
for (i = 0; i < N_MPC107_Regs; i++) {
printf (" 0x%x/%s = 0x%x\n",
MPC107Regs[i].iobase,
MPC107Regs[i].desc,
mpc824x_mpc107_getreg (MPC107Regs[i].iobase));
}
printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L));
printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U));
printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L));
printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U));
printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L));
printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U));
printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L));
printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U));
printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L));
printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U));
printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L));
printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U));
printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L));
printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U));
printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L));
printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U));
#endif /* INCLUDE_MPC107_REPORT */
#endif /* CONFIG_MOUSSE */
return (0);
}
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = mousse.o m48t59y.o pci.o flash.o
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#ifndef FLASH_LIB_H
#define FLASH_LIB_H
#include <common.h>
/* PIO operations max */
#define FLASH_PROGRAM_POLLS 100000
/* 10 Seconds default */
#define FLASH_ERASE_SECTOR_TIMEOUT (10*1000 /*SEC*/ )
/* Flash device info structure */
typedef struct flash_dev_s {
char name[24]; /* Bank Name */
int bank; /* Bank 0 or 1 */
unsigned int base; /* Base address */
int sectors; /* Sector count */
int lgSectorSize; /* Log2(usable bytes/sector) */
int vendorID; /* Expected vendor ID */
int deviceID; /* Expected device ID */
int found; /* Set if found by flashLibInit */
int swap; /* Set for bank 1 if byte swap req'd */
} flash_dev_t;
#define FLASH_MAX_POS(dev) \
((dev)->sectors << (dev)->lgSectorSize)
#define FLASH_SECTOR_POS(dev, sector) \
((sector) << (dev)->lgSectorSize)
/* AMD 29F040 */
#define FLASH0_BANK 0
#define FLASH0_VENDOR_ID 0x01
#define FLASH0_DEVICE_ID 0x49
/* AMD29LV160DB */
#define FLASH1_BANK 1
#define FLASH1_VENDOR_ID 0x0001
#define FLASH1_DEVICE_ID 0x2249
extern flash_dev_t flashDev[];
extern int flashDevCount;
/*
* Device pointers
*
* These must be kept in sync with the table in flashLib.c.
*/
#define FLASH_DEV_BANK0_SA0 (&flashDev[0])
#define FLASH_DEV_BANK0_SA1 (&flashDev[1])
#define FLASH_DEV_BANK0_SA2 (&flashDev[2])
#define FLASH_DEV_BANK0_LOW (&flashDev[3]) /* 960K */
#define FLASH_DEV_BANK0_BOOT (&flashDev[4]) /* PLCC */
#define FLASH_DEV_BANK0_HIGH (&flashDev[5]) /* 512K PLCC shadow */
unsigned long flash_init(void);
int flashEraseSector(flash_dev_t *dev, int sector);
int flashErase(flash_dev_t *dev);
int flashRead(flash_dev_t *dev, int pos, char *buf, int len);
int flashWrite(flash_dev_t *dev, int pos, char *buf, int len);
int flashWritable(flash_dev_t *dev, int pos, int len);
int flashDiag(flash_dev_t *dev);
int flashDiagAll(void);
ulong flash_get_size (vu_long *addr, flash_info_t *info);
void flash_print_info (flash_info_t *info);
int flash_erase (flash_info_t *info, int s_first, int s_last);
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
/*
* Flash info indices.
*/
#define FLASH_BANK_KERNEL 0
#define FLASH_BANK_BOOT 1
#define FLASH_BANK_AUX 2
#define FIRST_SECTOR 0
#endif /* !FLASH_LIB_H */
/*
* SGS M48-T59Y TOD/NVRAM Driver
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
*
* (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* SGS M48-T59Y TOD/NVRAM Driver
*
* The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and
* continuing for 8176 bytes. After that starts the Time-Of-Day (TOD)
* registers which are used to set/get the internal date/time functions.
*
* This module implements Y2K compliance by taking full year numbers
* and translating back and forth from the TOD 2-digit year.
*
* NOTE: for proper interaction with an operating system, the TOD should
* be used to store Universal Coordinated Time (GMT) and timezone
* conversions should be used.
*
* Here is a diagram of the memory layout:
*
* +---------------------------------------------+ 0xffe0a000
* | Non-volatile memory | .
* | | .
* | (8176 bytes of Non-volatile memory) | .
* | | .
* +---------------------------------------------+ 0xffe0bff0
* | Flags |
* +---------------------------------------------+ 0xffe0bff1
* | Unused |
* +---------------------------------------------+ 0xffe0bff2
* | Alarm Seconds |
* +---------------------------------------------+ 0xffe0bff3
* | Alarm Minutes |
* +---------------------------------------------+ 0xffe0bff4
* | Alarm Date |
* +---------------------------------------------+ 0xffe0bff5
* | Interrupts |
* +---------------------------------------------+ 0xffe0bff6
* | WatchDog |
* +---------------------------------------------+ 0xffe0bff7
* | Calibration |
* +---------------------------------------------+ 0xffe0bff8
* | Seconds |
* +---------------------------------------------+ 0xffe0bff9
* | Minutes |
* +---------------------------------------------+ 0xffe0bffa
* | Hours |
* +---------------------------------------------+ 0xffe0bffb
* | Day |
* +---------------------------------------------+ 0xffe0bffc
* | Date |
* +---------------------------------------------+ 0xffe0bffd
* | Month |
* +---------------------------------------------+ 0xffe0bffe
* | Year (2 digits only) |
* +---------------------------------------------+ 0xffe0bfff
*/
#include <common.h>
#include <rtc.h>
#include "mousse.h"
/*
* Imported from mousse.h:
*
* TOD_REG_BASE Base of m48t59y TOD registers
* SYS_TOD_UNPROTECT() Disable NVRAM write protect
* SYS_TOD_PROTECT() Re-enable NVRAM write protect
*/
#define YEAR 0xf
#define MONTH 0xe
#define DAY 0xd
#define DAY_OF_WEEK 0xc
#define HOUR 0xb
#define MINUTE 0xa
#define SECOND 0x9
#define CONTROL 0x8
#define WATCH 0x7
#define INTCTL 0x6
#define WD_DATE 0x5
#define WD_HOUR 0x4
#define WD_MIN 0x3
#define WD_SEC 0x2
#define _UNUSED 0x1
#define FLAGS 0x0
#define M48_ADDR ((volatile unsigned char *) TOD_REG_BASE)
int m48_tod_init(void)
{
SYS_TOD_UNPROTECT();
M48_ADDR[CONTROL] = 0;
M48_ADDR[WATCH] = 0;
M48_ADDR[INTCTL] = 0;
/*
* If the oscillator is currently stopped (as on a new part shipped
* from the factory), start it running.
*
* Here is an example of the TOD bytes on a brand new M48T59Y part:
* 00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01
*/
if (M48_ADDR[SECOND] & 0x80)
M48_ADDR[SECOND] = 0;
/* Is battery low */
if ( M48_ADDR[FLAGS] & 0x10) {
printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n");
}
SYS_TOD_PROTECT();
return 0;
}
/*
* m48_tod_set
*/
static int to_bcd(int value)
{
return value / 10 * 16 + value % 10;
}
static int from_bcd(int value)
{
return value / 16 * 10 + value % 16;
}
static int day_of_week(int y, int m, int d) /* 0-6 ==> Sun-Sat */
{
static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4};
y -= m < 3;
return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7;
}
/*
* Note: the TOD should store the current GMT
*/
int m48_tod_set(int year, /* 1980-2079 */
int month, /* 01-12 */
int day, /* 01-31 */
int hour, /* 00-23 */
int minute, /* 00-59 */
int second) /* 00-59 */
{
SYS_TOD_UNPROTECT();
M48_ADDR[CONTROL] |= 0x80; /* Set WRITE bit */
M48_ADDR[YEAR] = to_bcd(year % 100);
M48_ADDR[MONTH] = to_bcd(month);
M48_ADDR[DAY] = to_bcd(day);
M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1;
M48_ADDR[HOUR] = to_bcd(hour);
M48_ADDR[MINUTE] = to_bcd(minute);
M48_ADDR[SECOND] = to_bcd(second);
M48_ADDR[CONTROL] &= ~0x80; /* Clear WRITE bit */
SYS_TOD_PROTECT();
return 0;
}
/*
* Note: the TOD should store the current GMT
*/
int m48_tod_get(int *year, /* 1980-2079 */
int *month, /* 01-12 */
int *day, /* 01-31 */
int *hour, /* 00-23 */
int *minute, /* 00-59 */
int *second) /* 00-59 */
{
int y;
SYS_TOD_UNPROTECT();
M48_ADDR[CONTROL] |= 0x40; /* Set READ bit */
y = from_bcd(M48_ADDR[YEAR]);
*year = y < 80 ? 2000 + y : 1900 + y;
*month = from_bcd(M48_ADDR[MONTH]);
*day = from_bcd(M48_ADDR[DAY]);
/* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */
*hour = from_bcd(M48_ADDR[HOUR]);
*minute = from_bcd(M48_ADDR[MINUTE]);
*second = from_bcd(M48_ADDR[SECOND] & 0x7f);
M48_ADDR[CONTROL] &= ~0x40; /* Clear READ bit */
SYS_TOD_PROTECT();
return 0;
}
int m48_tod_get_second(void)
{
return from_bcd(M48_ADDR[SECOND] & 0x7f);
}
/*
* Watchdog function
*
* If usec is 0, the watchdog timer is disarmed.
*
* If usec is non-zero, the watchdog timer is armed (or re-armed) for
* approximately usec microseconds (if the exact requested usec is
* not supported by the chip, the next higher available value is used).
*
* Minimum watchdog timeout = 62500 usec
* Maximum watchdog timeout = 124 sec (124000000 usec)
*/
void m48_watchdog_arm(int usec)
{
int mpy, res;
SYS_TOD_UNPROTECT();
if (usec == 0) {
res = 0;
mpy = 0;
} else if (usec < 2000000) { /* Resolution: 1/16s if below 2s */
res = 0;
mpy = (usec + 62499) / 62500;
} else if (usec < 8000000) { /* Resolution: 1/4s if below 8s */
res = 1;
mpy = (usec + 249999) / 250000;
} else if (usec < 32000000) { /* Resolution: 1s if below 32s */
res = 2;
mpy = (usec + 999999) / 1000000;
} else { /* Resolution: 4s up to 124s */
res = 3;
mpy = (usec + 3999999) / 4000000;
if (mpy > 31)
mpy = 31;
}
M48_ADDR[WATCH] = (0x80 | /* Steer to RST signal (IRQ = N/C) */
mpy << 2 |
res);
SYS_TOD_PROTECT();
}
/*
* U-Boot RTC support.
*/
int
rtc_get( struct rtc_time *tmp )
{
m48_tod_get(&tmp->tm_year,
&tmp->tm_mon,
&tmp->tm_mday,
&tmp->tm_hour,
&tmp->tm_min,
&tmp->tm_sec);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
#ifdef RTC_DEBUG
printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
#endif
return 0;
}
int rtc_set( struct rtc_time *tmp )
{
m48_tod_set(tmp->tm_year, /* 1980-2079 */
tmp->tm_mon, /* 01-12 */
tmp->tm_mday, /* 01-31 */
tmp->tm_hour, /* 00-23 */
tmp->tm_min, /* 00-59 */
tmp->tm_sec); /* 00-59 */
#ifdef RTC_DEBUG
printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
return 0;
}
void
rtc_reset (void)
{
m48_tod_init();
}
/*
* SGS M48-T59Y TOD/NVRAM Driver
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
*
* (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __M48_T59_Y_H
#define __M48_T59_Y_H
/*
* M48 T59Y -Timekeeping Battery backed SRAM.
*/
int m48_tod_init(void);
int m48_tod_set(int year,
int month,
int day,
int hour,
int minute,
int second);
int m48_tod_get(int *year,
int *month,
int *day,
int *hour,
int *minute,
int *second);
int m48_tod_get_second(void);
void m48_watchdog_arm(int usec);
#endif /*!__M48_T59_Y_H */
/*
* MOUSSE Board Support
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2001
* James Dougherty, jfd@cs.stanford.edu
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc824x.h>
#include <netdev.h>
#include <asm/processor.h>
#include <timestamp.h>
#include "mousse.h"
#include "m48t59y.h"
#include <pci.h>
int checkboard (void)
{
ulong busfreq = get_bus_freq (0);
char buf[32];
puts ("Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B)\n");
printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
printf ("MPLD: Revision %d\n", SYS_REVID_GET ());
printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq));
return 0;
}
int checkflash (void)
{
printf ("checkflash\n");
flash_init ();
return 0;
}
phys_size_t initdram (int board_type)
{
return CONFIG_SYS_RAM_SIZE;
}
void get_tod (void)
{
int year, month, day, hour, minute, second;
m48_tod_get (&year, &month, &day, &hour, &minute, &second);
printf (" Current date/time: %d/%d/%d %d:%d:%d \n",
month, day, year, hour, minute, second);
}
/*
* EPIC, PCI, and I/O devices.
* Initialize Mousse Platform, probe for PCI devices,
* Query configuration parameters if not set.
*/
int misc_init_f (void)
{
m48_tod_init (); /* Init SGS M48T59Y TOD/NVRAM */
printf ("RTC: M48T589 TOD/NVRAM (%d) bytes\n", TOD_NVRAM_SIZE);
get_tod ();
return 0;
}
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}
/*
* MOUSSE/MPC8240 Board definitions.
* For more info, see http://www.vooha.com/
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2001
* James Dougherty (jfd@cs.stanford.edu)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MOUSSE_H
#define __MOUSSE_H
/* System addresses */
#define PCI_SPECIAL_BASE 0xfe000000
#define PCI_SPECIAL_SIZE 0x01000000
/* PORTX Device Addresses for Mousse */
#define PORTX_DEV_BASE 0xff000000
#define PORTX_DEV_SIZE 0x01000000
#define ENET_DEV_BASE 0x80000000
#define PLD_REG_BASE (PORTX_DEV_BASE | 0xe09000)
#define PLD_REG(off) (*(volatile unsigned char *) \
(PLD_REG_BASE + (off)))
#define PLD_REVID_B1 0x7f
#define PLD_REVID_B2 0x01
/* MPLD */
#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */
#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f)
#define SYS_LED_OFF() (PLD_REG(1) |= 0x80)
#define SYS_LED_ON() (PLD_REG(1) &= ~0x80)
#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80)
#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80)
#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80)
#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80)
/* SGS M48T59Y */
#define TOD_BASE (PORTX_DEV_BASE | 0xe0a000)
#define TOD_REG_BASE (TOD_BASE | 0x1ff0)
#define TOD_NVRAM_BASE TOD_BASE
#define TOD_NVRAM_SIZE 0x1ff0
#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE)
/* NS16552 SIO */
#define SERIAL_BASE(_x) (PORTX_DEV_BASE | 0xe08000 | ((_x) ? 0 : 0x80))
#define N_SIO_CHANNELS 2
#define N_COM_PORTS N_SIO_CHANNELS
/*
* On-board Dec21143 PCI Ethernet
* Note: The PCI MBAR chosen here was used from MPC8240UM which states
* that PCI memory is at: 0x80000 - 0xFDFFFFFF, if AMBOR[CPU_FD_ALIAS]
* is set, then PCI memory maps 1-1 with this address range in the
* correct byte order.
*/
#define PCI_ENET_IOADDR 0x80000000
#define PCI_ENET_MEMADDR 0x80000000
/*
* Flash Memory Layout
*
* 2 MB Flash Bank 0 runs in 8-bit mode. In Flash Bank 0, the 32 kB
* sector SA3 is obscured by the 32 kB serial/TOD access space, and
* the 64 kB sectors SA19-SA26 are obscured by the 512 kB PLCC
* containing the fixed boot ROM. (If the 512 kB PLCC is
* deconfigured by jumper, this window to Flash Bank 0 becomes
* visible, but it still contains the fixed boot code and should be
* considered read-only). Flash Bank 0 sectors SA0 (16 kB), SA1 (8
* kB), and SA2 (8 kB) are currently unused.
*
* 2 MB Flash Bank 1 runs in 16-bit mode. Flash Bank 1 is fully
* usable, but it's a 16-bit wide device on a 64-bit bus. Therefore
* 16-bit words only exist at addresses that are multiples of 8. All
* PROM data and control addresses must be multiplied by 8.
*
* See flashMap.c for description of flash filesystem layout.
*/
/*
* FLASH memory address space: 8-bit wide FLASH memory spaces.
*/
#define FLASH0_SEG0_START 0xffe00000 /* Baby 32Kb segment */
#define FLASH0_SEG0_END 0xffe07fff /* 16 kB + 8 kB + 8 kB */
#define FLASH0_SEG0_SIZE 0x00008000 /* (sectors SA0-SA2) */