Commit 03f9d7d1 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Tom Rini

mpc8xx: remove fads board support

These boards are old enough and have no maintainers.
Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
parent c51c1c9a
......@@ -56,9 +56,6 @@
GOT_ENTRY(__init_end)
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
#if defined(CONFIG_FADS)
GOT_ENTRY(environment)
#endif
END_GOT
/*
......
......@@ -97,14 +97,8 @@ static int check_CPU (long clock, uint pvr, uint immr)
pre = 'M'; m = 1;
if (id_str == NULL)
id_str =
# if defined(CONFIG_MPC852T)
"PC852T";
# elif defined(CONFIG_MPC859T)
# if defined(CONFIG_MPC859T)
"PC859T";
# elif defined(CONFIG_MPC859DSL)
"PC859DSL";
# elif defined(CONFIG_MPC866T)
"PC866T";
# else
"PC866x"; /* Unknown chip from MPC866 family */
# endif
......
......@@ -542,32 +542,6 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
(volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
int i;
if (efis->ether_index == 0) {
#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
#if defined(CONFIG_MPC885ADS)
*(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
#else
/* configure FADS for fast (FEC) ethernet, half-duplex */
/* The LXT970 needs about 50ms to recover from reset, so
* wait for it by discovering the PHY before leaving eth_init().
*/
{
volatile uint *bcsr4 = (volatile uint *) BCSR4;
*bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
| (BCSR4_FETHCFG0 | BCSR4_FETHFDE |
BCSR4_FETHRST);
/* reset the LXT970 PHY */
*bcsr4 &= ~BCSR4_FETHRST;
udelay (10);
*bcsr4 |= BCSR4_FETHRST;
udelay (10);
}
#endif /* CONFIG_MPC885ADS */
#endif /* CONFIG_FADS */
}
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/* the MII interface is connected to FEC1
* so for the miiphy_xxx function to work we must
......
......@@ -197,19 +197,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
reset_phy();
#endif
#ifdef CONFIG_FADS
#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
/* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
*((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#else
*((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#endif
#endif
pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
rxIdx = 0;
......@@ -488,13 +475,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
/*
* Work around transmit problem with first eth packet
*/
#if defined (CONFIG_FADS)
udelay (10000); /* wait 10 ms */
#endif
return 1;
}
......
......@@ -173,15 +173,6 @@ static int smc_init (void)
# endif
#endif
#if defined(CONFIG_FADS)
/* Enable RS232 */
#if defined(CONFIG_8xx_CONS_SMC1)
*((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
#else
*((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
#endif
#endif /* CONFIG_FADS */
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
......
......@@ -798,22 +798,6 @@ static void video_encoder_init (void)
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
#ifdef CONFIG_FADS
/* Reset ADV7176 chip */
debug ("[VIDEO ENCODER] Resetting encoder...\n");
(*(int *) BCSR4) &= ~(1 << 21);
/* Wait for 5 ms inside the reset */
debug ("[VIDEO ENCODER] Waiting for encoder reset...\n");
udelay (5000);
/* Take ADV7176 out of reset */
(*(int *) BCSR4) |= 1 << 21;
/* Wait for 5 ms after the reset */
udelay (5000);
#endif /* CONFIG_FADS */
/* Send configuration */
#ifdef DEBUG
{
......@@ -860,16 +844,6 @@ static void video_ctrl_init (void *memptr)
debug ("[VIDEO CTRL] Turning off video controller...\n");
SETBIT (immap->im_vid.vid_vccr, VIDEO_VCCR_VON, 0);
#ifdef CONFIG_FADS
/* Turn on Video Port LED */
debug ("[VIDEO CTRL] Turning off video port led...\n");
SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 1);
/* Disable internal clock */
debug ("[VIDEO CTRL] Disabling internal clock...\n");
SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 0);
#endif
/* Generate and make active a new video mode */
debug ("[VIDEO CTRL] Generating video mode...\n");
video_mode_generate ();
......@@ -892,15 +866,6 @@ static void video_ctrl_init (void *memptr)
immap->im_ioport.iop_pdpar = 0x1fff;
immap->im_ioport.iop_pddir = 0x0000;
#ifdef CONFIG_FADS
/* Turn on Video Port Clock - ONLY AFTER SET VCCR TO ENABLE EXTERNAL CLOCK */
debug ("[VIDEO CTRL] Turning on video clock...\n");
SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 1);
/* Turn on Video Port LED */
debug ("[VIDEO CTRL] Turning on video port led...\n");
SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 0);
#endif
#ifdef CONFIG_RRVISION
debug ("PC5->Output(1): enable PAL clock");
immap->im_ioport.iop_pcpar &= ~(0x0400);
......@@ -1153,9 +1118,7 @@ static void *video_logo (void)
{
u16 *screen = video_fb_address, width = VIDEO_COLS;
#ifdef VIDEO_INFO
# ifndef CONFIG_FADS
char temp[32];
# endif
char info[80];
#endif /* VIDEO_INFO */
......@@ -1173,7 +1136,7 @@ static void *video_logo (void)
sprintf (info, " Wolfgang DENK, wd@denx.de");
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2,
info);
#ifndef CONFIG_FADS /* all normal boards */
/* leave one blank line */
sprintf(info, "MPC823 CPU at %s MHz, %ld MiB RAM, %ld MiB Flash",
......@@ -1182,15 +1145,6 @@ static void *video_logo (void)
gd->bd->bi_flashsize >> 20 );
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 4,
info);
#else /* FADS :-( */
sprintf (info, "MPC823 CPU at 50 MHz on FADS823 board");
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT,
info);
sprintf(info, "2MiB FLASH - 8MiB DRAM - 4MiB SRAM");
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2,
info);
#endif
#endif
return video_fb_address + VIDEO_LOGO_HEIGHT * VIDEO_LINE_LEN;
......
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = fads.o flash.o lamp.o pcmcia.o
/*
* (C) Copyright 2000
* Dave Ellis, SIXNET, dge@sixnetio.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
Using the Motorola MPC8XXFADS development board
===============================================
CONFIGURATIONS
--------------
There are ready-to-use default configurations available for the
FADS823, FADS850SAR and FADS860T. The FADS860T configuration also
works for the 855T processor.
LOADING U-Boot INTO FADS FLASH MEMORY
--------------------------------------
MPC8BUG can load U-Boot into the FLASH memory using LOADF.
loadf u-boot.srec 100000
STARTING U-Boot FROM MPC8BUG
-----------------------------
To start U-Boot from MPC8BUG:
1. Reset the board:
reset :h
2. Change BR0 and OR0 back to their values at reset:
rms memc br0 00000001
rms memc or0 00000d34
3. Modify DER so MPC8BUG gets control only when it should:
rms der 2002000f
4. Start as if from reset:
go 100
This is NOT exactly the same as starting U-Boot without
MPC8BUG. MPC8BUG turns off the watchdog as part of the hard reset.
After it does the reset it writes SYPCR (to disable the watchdog)
and sets BR0 and OR0 to map the FLASH at 0x02800000 (and does lots
of other initialization). That is why it is necessary to set BR0
and OR0 to map the FLASH everywhere. U-Boot can't turn on the
watchdog after that, since MPC8BUG has used the only chance to write
to SYPCR.
Here is a bizarre sequence of MPC8BUG and U-Boot commands that lets
U-Boot write to SYPCR. It works with MPC8BUG 1.5 and an 855T
processor (your mileage may vary). It is probably better (and a lot
easier) just to accept having the watchdog disabled when the debug
cable is connected.
in MPC8BUG:
reset :h
rms memc br0 00000001
rms memc or0 00000d34
rms der 2000f
go 100
Now U-Boot is running with the MPC8BUG value for SYPCR. Use the
U-Boot 'reset' command to reset the board.
=>reset
Next, in MPC8BUG:
rms der 2000f
go
Now U-Boot is running with the U-Boot value for SYPCR.
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#include <config.h>
#include <common.h>
void
signal_delay(unsigned int n)
{
while (n--);
}
void
signal_on(void)
{
*((volatile uint *)BCSR4) &= ~(1<<(31-3)); /* led on */
}
void
signal_off(void)
{
*((volatile uint *)BCSR4) |= (1<<(31-3)); /* led off */
}
void
slow_blink(unsigned int n)
{
while (n--) {
signal_on();
signal_delay(0x00400000);
signal_off();
signal_delay(0x00400000);
}
}
void
fast_blink(unsigned int n)
{
while (n--) {
signal_on();
signal_delay(0x00100000);
signal_off();
signal_delay(0x00100000);
}
}
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if defined(CONFIG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "FADS"
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
u_long reg = 0;
switch(vpp) {
case 0: reg = 0; break;
case 50: reg = 1; break;
case 120: reg = 2; break;
default: return 1;
}
switch(vcc) {
case 0: reg = 0; break;
#ifdef CONFIG_FADS
case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break;
case 50: reg = BCSR1_PCCVCC1; break;
#endif
default: return 1;
}
/* first, turn off all power */
#ifdef CONFIG_FADS
*((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1);
#endif
*((uint *)BCSR1) &= ~BCSR1_PCCVPP_MASK;
/* enable new powersettings */
#ifdef CONFIG_FADS
*((uint *)BCSR1) |= reg;
#endif
*((uint *)BCSR1) |= reg << 20;
return 0;
}
int pcmcia_hardware_enable(int slot)
{
*((uint *)BCSR1) &= ~BCSR1_PCCEN;
return 0;
}
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
*((uint *)BCSR1) &= ~BCSR1_PCCEN;
return 0;
}
#endif
#endif /* CONFIG_PCMCIA */
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
/*. = DEFINED(env_offset) ? env_offset : .;*/
common/env_embedded.o (.ppcenv*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)
......@@ -982,8 +982,6 @@ Active powerpc mpc8xx - - -
Active powerpc mpc8xx - - - v37 - -
Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au>
Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com>
Active powerpc mpc8xx - - fads MPC86xADS - -
Active powerpc mpc8xx - - fads MPC885ADS - -
Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - icu862 ICU862_100MHz ICU862:100MHz Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - ip860 IP860 - Wolfgang Denk <wd@denx.de>
......
......@@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
fads powerpc mpc8xx - -
netphone powerpc mpc8xx - -
netta2 powerpc mpc8xx - -
netta powerpc mpc8xx - -
......
......@@ -28,10 +28,8 @@ typedef volatile unsigned char vu_char;
#endif
#if defined(CONFIG_8xx)
#include <asm/8xx_immap.h>
#if defined(CONFIG_MPC852) || defined(CONFIG_MPC852T) || \
defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \
defined(CONFIG_MPC859DSL) || \
defined(CONFIG_MPC866) || defined(CONFIG_MPC866T) || \
#if defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \
defined(CONFIG_MPC866) || \
defined(CONFIG_MPC866P)
# define CONFIG_MPC866_FAMILY 1
#elif defined(CONFIG_MPC870) \
......
......@@ -531,45 +531,6 @@ typedef struct scc_enet {
#endif
/*** FADS860T********************************************************/
#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x)
/*
* This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1.
*/
#ifdef CONFIG_SCC1_ENET
#define SCC_ENET 0
#define PROFF_ENET PROFF_SCC1
#define CPM_CR_ENET CPM_CR_CH_SCC1
#define PA_ENET_RXD ((ushort)0x0001)
#define PA_ENET_TXD ((ushort)0x0002)
#define PA_ENET_TCLK ((ushort)0x0100)
#define PA_ENET_RCLK ((ushort)0x0200)
#define PB_ENET_TENA ((uint)0x00001000)
#define PC_ENET_CLSN ((ushort)0x0010)
#define PC_ENET_RENA ((ushort)0x0020)
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000002c)
#endif /* CONFIG_SCC1_ETHERNET */
/*
* This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
* with ethernet on FEC.
*/
#ifdef CONFIG_FEC_ENET
#define FEC_ENET /* Use FEC for Ethernet */
#endif /* CONFIG_FEC_ENET */
#endif /* CONFIG_FADS && CONFIG_MPC86x */
/*** FPS850L, FPS860L ************************************************/
#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
......
/*
* A collection of structures, addresses, and values associated with
* the Motorola MPC8xxADS board. Copied from the FADS config.
*
* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
*
* Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
*
* Values common to all FADS family boards are in board/fads/fads.h
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
/* board type */
#define CONFIG_MPC86xADS 1 /* new ADS */
#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
/* CPU type - pick one of these */
#define CONFIG_MPC866T 1
#undef CONFIG_MPC866P
#undef CONFIG_MPC859T
#undef CONFIG_MPC859DSL
#undef CONFIG_MPC852T
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 38400
#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000
#define CONFIG_SYS_8xx_CPUCLK_MAX 80000000
#define CONFIG_DRAM_50MHZ 1
#define CONFIG_SDRAM_50MHZ 1
#include "../../board/fads/fads.h"
#define CONFIG_SYS_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */
#define CONFIG_SYS_BR5_PRELIM (CONFIG_SYS_PHYDEV_ADDR | BR_PS_8 | BR_V)
#endif /* __CONFIG_H */
/*
* A collection of structures, addresses, and values associated with
* the Motorola MPC885ADS board. Values common to all FADS family boards
* are in board/fads/fads.h
*
* Copyright (C) 2003-2004 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MPC885ADS 1 /* MPC885ADS board */
#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 38400
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000
#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
#define CONFIG_SDRAM_50MHZ 1
#include "../../board/fads/fads.h"
#define CONFIG_SYS_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */
#define CONFIG_SYS_BR5_PRELIM (CONFIG_SYS_PHYDEV_ADDR | BR_PS_8 | BR_V)
#define CONFIG_HAS_ETH1
#endif /* __CONFIG_H */
......@@ -21,13 +21,7 @@
#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
#if defined(CONFIG_FADS) /* The FADS series are a mess */
# if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821)
# define CONFIG_PCMCIA_SLOT_A
# else
# define CONFIG_PCMCIA_SLOT_B
# endif
#elif defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)
#if defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)
# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
#elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */
# define CONFIG_PCMCIA_SLOT_B
......
......@@ -114,19 +114,6 @@ static void scc_init (int scc_index)
immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
#if defined(CONFIG_FADS)
#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC86xADS)
/* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */
*((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#else
*((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#endif
#endif
pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]);
rxIdx = 0;
......@@ -371,13 +358,6 @@ static void scc_init (int scc_index)
immr->im_cpm.cp_scc[scc_index].scc_gsmrl |=
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
/*
* Work around transmit problem with first eth packet
*/
#if defined (CONFIG_FADS)
udelay (10000); /* wait 10 ms */
#endif
}
static void scc_halt (int scc_index)
......
......@@ -100,12 +100,6 @@ static void smc_init (int smc_index)
im->im_sdma.sdma_sdmr = 0x00;
#endif
#if defined(CONFIG_FADS)
/* Enable RS232 */
*((uint *) BCSR1) &=
~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
#endif
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
......
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