Commit 055ce080 authored by Timur Tabi's avatar Timur Tabi Committed by Andy Fleming

powerpc/85xx: remove support for the Freescale P3060

The P3060 was cancelled before it went into production, so there's no point
in supporting it.
Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
parent 61fc52b6
......@@ -65,7 +65,6 @@ COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P2040) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3060) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
COBJS-$(CONFIG_BSC9131) += ddr-gen3.o
......@@ -81,7 +80,6 @@ COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o
COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
COBJS-$(CONFIG_PPC_P3060) += p3060_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
......@@ -113,7 +111,6 @@ COBJS-$(CONFIG_P2020) += p2020_serdes.o
COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
COBJS-$(CONFIG_PPC_P3060) += p3060_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
......
......@@ -534,7 +534,7 @@ void fdt_fixup_fman_firmware(void *blob)
#define fdt_fixup_fman_firmware(x)
#endif
#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060)
#if defined(CONFIG_PPC_P4080)
static void fdt_fixup_usb(void *fdt)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
......
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO( 1, 2, 1, 0),
SET_QP_INFO( 3, 4, 2, 1),
SET_QP_INFO( 5, 6, 3, 2),
SET_QP_INFO( 7, 8, 4, 3),
SET_QP_INFO( 9, 10, 5, 4),
SET_QP_INFO(11, 12, 6, 5),
SET_QP_INFO(13, 14, 7, 6),
SET_QP_INFO(15, 16, 8, 7),
SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */
SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
};
#endif
struct srio_liodn_id_table srio_liodn_tbl[] = {
SET_SRIO_LIODN_1(1, 198),
SET_SRIO_LIODN_1(2, 199),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
struct liodn_id_table liodn_tbl[] = {
SET_USB_LIODN(1, "fsl-usb2-mph", 127),
SET_USB_LIODN(2, "fsl-usb2-dr", 157),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
SET_DMA_LIODN(1, 196),
SET_DMA_LIODN(2, 197),
SET_GUTS_LIODN("fsl,srio-rmu", 200, rmuliodnr, 0xd3000),
#ifdef CONFIG_SYS_DPAA_QBMAN
SET_QMAN_LIODN(31),
SET_BMAN_LIODN(32),
#endif
SET_PME_LIODN(128),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN
struct liodn_id_table fman1_liodn_tbl[] = {
SET_FMAN_RX_1G_LIODN(1, 0, 11),
SET_FMAN_RX_1G_LIODN(1, 1, 12),
SET_FMAN_RX_1G_LIODN(1, 2, 13),
SET_FMAN_RX_1G_LIODN(1, 3, 14),
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#if (CONFIG_SYS_NUM_FMAN == 2)
struct liodn_id_table fman2_liodn_tbl[] = {
SET_FMAN_RX_1G_LIODN(2, 0, 16),
SET_FMAN_RX_1G_LIODN(2, 1, 17),
SET_FMAN_RX_1G_LIODN(2, 2, 18),
SET_FMAN_RX_1G_LIODN(2, 3, 19),
};
int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
#endif
#endif
struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(0, 146, 154),
SET_SEC_JR_LIODN_ENTRY(1, 147, 155),
SET_SEC_JR_LIODN_ENTRY(2, 178, 186),
SET_SEC_JR_LIODN_ENTRY(3, 179, 187),
SET_SEC_RTIC_LIODN_ENTRY(a, 144),
SET_SEC_RTIC_LIODN_ENTRY(b, 145),
SET_SEC_RTIC_LIODN_ENTRY(c, 176),
SET_SEC_RTIC_LIODN_ENTRY(d, 177),
SET_SEC_DECO_LIODN_ENTRY(0, 129, 161),
SET_SEC_DECO_LIODN_ENTRY(1, 130, 162),
SET_SEC_DECO_LIODN_ENTRY(2, 131, 163),
SET_SEC_DECO_LIODN_ENTRY(3, 132, 164),
SET_SEC_DECO_LIODN_ENTRY(4, 133, 165),
};
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
struct liodn_id_table liodn_bases[] = {
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106),
#ifdef CONFIG_SYS_DPAA_FMAN
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
#if (CONFIG_SYS_NUM_FMAN == 2)
[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64),
#endif
#endif
#ifdef CONFIG_SYS_DPAA_PME
[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(116, 133),
#endif
};
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <asm/processor.h>
#include <asm/io.h>
#include "fsl_corenet_serdes.h"
static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
[0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC1,
SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2,
NONE, NONE, AURORA, AURORA},
[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SGMII_FM2_DTSEC3,
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4,
SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM1_DTSEC2, NONE, NONE, AURORA, AURORA},
[0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
[0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, PCIE2, PCIE2, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
[0x1c] = {NONE, NONE, SRIO1, SRIO2, NONE, NONE, NONE, NONE,
AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
};
enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
{
if (!serdes_lane_enabled(lane))
return NONE;
return serdes_cfg_tbl[cfg][lane];
}
int is_serdes_prtcl_valid(u32 prtcl)
{
int i;
if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
if (serdes_cfg_tbl[prtcl][i] != NONE)
return 1;
}
return 0;
}
void soc_serdes_init(void)
{
/*
* On the P3060 the devdisr2 register does not correctly reflect
* the state of the MACs based on the RCW fields. So disable the MACs
* based on the srds_prtcl and ec1, ec2, ec3 fields
*/
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
/* NOTE: Leave FM1-1,FM1-2 alone for MDIO access */
if (!is_serdes_configured(SGMII_FM1_DTSEC3))
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_3;
if (!is_serdes_configured(SGMII_FM1_DTSEC4))
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_4;
if (!is_serdes_configured(SGMII_FM2_DTSEC1))
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_1;
if (!is_serdes_configured(SGMII_FM2_DTSEC2))
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_2;
if (!is_serdes_configured(SGMII_FM2_DTSEC3))
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_3;
if (!is_serdes_configured(SGMII_FM2_DTSEC4))
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_4;
if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) {
devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_2;
}
if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1) {
devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_1;
}
out_be32(&gur->devdisr2, devdisr2);
}
......@@ -69,7 +69,6 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(P2040, P2040, 4),
CPU_TYPE_ENTRY(P2041, P2041, 4),
CPU_TYPE_ENTRY(P3041, P3041, 4),
CPU_TYPE_ENTRY_MASK(P3060, P3060, 6, 0xf3),
CPU_TYPE_ENTRY(P4040, P4040, 4),
CPU_TYPE_ENTRY(P4080, P4080, 8),
CPU_TYPE_ENTRY(P5010, P5010, 1),
......
......@@ -379,25 +379,6 @@
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P3060)
#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM2_DTSEC 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P4040)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
......
......@@ -1766,7 +1766,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060)
#ifdef CONFIG_PPC_P4080
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
......
......@@ -1087,7 +1087,6 @@
#define SVR_P2040 0x821000
#define SVR_P2041 0x821001
#define SVR_P3041 0x821103
#define SVR_P3060 0x820002
#define SVR_P4040 0x820100
#define SVR_P4080 0x820000
#define SVR_P5010 0x822100
......
......@@ -51,14 +51,12 @@ COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o
COBJS-$(CONFIG_P1022DS) += ics307_clk.o
COBJS-$(CONFIG_P2020DS) += ics307_clk.o
COBJS-$(CONFIG_P3041DS) += ics307_clk.o
COBJS-$(CONFIG_P3060QDS) += ics307_clk.o
COBJS-$(CONFIG_P4080DS) += ics307_clk.o
COBJS-$(CONFIG_P5020DS) += ics307_clk.o
# deal with common files for P-series corenet based devices
SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3060QDS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o
......
#
# Copyright 2011 Freescale Semiconductor, Inc.
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += eth.o
COBJS-y += fixed_ddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
Overview
=========
The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC.
The P3060 Processor combines six e500mc Power Architecture processor
cores(1.2GHz) with high-performance datapath acceleration
architecture(DPAA), CoreNet fabric infrastructure, as well as network
and peripheral bus interfaces required for networking, telecom/datacom,
wireless infrastructure, and military/aerospace applications.
P3060QDS Board Specifications:
==============================
Memory subsystem:
* 2G Bytes UDIMM DDR3(64bit bus) with ECC on
* 128M Bytes NOR flash single-chip memory
* 16M Bytes SPI flash
* 8K Bytes AT24C64 I2C EEPROM for RCW
Ethernet(Default SERDES 0x19):
* FM1-dTSEC1: connected to RGMII PHY1 (Vitesse VSC8641 on board,Bottom of dual RJ45)
* FM1-dTSEC2: connected to RGMII PHY2 (Vitesse VSC8641 on board,Top of dual RJ45)
* FM1-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port1 in slot1)
* FM1-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port3 in slot1)
* FM2-dTSEC1: connected to SGMII PHY (Vitesse VSC8234 port0 in slot2)
* FM2-dTSEC2: connected to SGMII PHY (Vitesse VSC8234 port2 in slot2)
* FM2-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port0 in slot1)
* FM2-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port2 in slot1)
PCIe:
* PCIe1: Lanes A, B, C and D of Bank1 are connected to one x4 PCIe SLOT4
* PCIe2: Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT3
RapidIO:
* sRIO1: Lanes E, F, G and H of Bank1 are connected to sRIO1 (SLOT3)
* sRIO2: Lanes A, B, C and D of Bank1 are connected to sRIO2 (SLOT4)
USB:
* USB1: connected via an external ULPI PHY SMC3315 to a TYPE-A interface
* USB2: connected via an external ULPI PHY SMC3315 to a TYPE-AB interface
I2C:
* I2C1_CH0: EEPROM AT24C64(0x50) RCW, AT24C02(0x51) DDR SPD,
AT24C02(0x53) DDR SPD, AT24C02(0x57) SystemID, RTC DS3232(0x68)
* I2C1_CH1: 1588 RiserCard(0x55), HSLB Testport, TempMon
ADT7461(0x4C), SerDesMux DS64MB201(0x51/59/5C/5D)
* I2C1_CH2: VDD/GVDD/GIDD ZL6100 (0x21/0x22/0x23/0x24/0x40)
* I2C1_CH3: OCM CFG AT24C02(0x55), OCM IPL AT24C64(0x56)
* I2C1_CH4: PCIe SLOT1
* I2C1_CH5: PCIe SLOT2
* I2C1_CH6: PCIe SLOT3
* I2C1_CH7: PCIe SLOT4
* I2C2: NULL
* I2C3: NULL
UART:
* Supports two UARTs up to 115200 bps for console
Boot from NOR flash
===================
1. Build image
export ARCH=powerpc
export CROSS_COMPILE=/your_path/gcc-4.5.xx-eglibc-2.11.xx/powerpc-linux-gnu/bin/powerpc-linux-gnu-
make P3060QDS_config
make
2. Program image
=> tftp 1000000 u-boot.bin
=> protect off all
=> erase eff80000 efffffff
=> cp.b 1000000 eff80000 80000
3. Program RCW
=> tftp 1000000 rcw.bin
=> protect off all
=> erase e8000000 e801ffff
=> cp.b 1000000 e8000000 50
4. Program FMAN Firmware ucode
=> tftp 1000000 ucode.bin
=> protect off all
=> erase ef000000 ef0fffff
=> cp.b 1000000 ef000000 2000
5. Change DIP-switch
RCW Location: SW1[1-5] = 01101 (eLBC 16bit NOR flash)
Note: 1 stands for 'on', 0 stands for 'off'
Using the Device Tree Source File
=================================
To create the DTB (Device Tree Binary) image file, use a command
similar to this:
dtc -O dtb -b 0 -p 1024 p3060qds.dts > p3060qds.dtb
Or use the following command:
{linux-2.6}/make p3060qds.dtb ARCH=powerpc
then the dtb file will be generated under the following directory:
{linux-2.6}/arch/powerpc/boot/p3060qds.dtb
Booting Linux
=============
Place a linux uImage in the TFTP disk area.
tftp 1000000 uImage
tftp 2000000 rootfs.ext2.gz.uboot
tftp 3000000 p3060rdb.dtb
bootm 1000000 2000000 3000000
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "p3060qds.h"
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
phys_size_t fixed_sdram(void)
{
int i;
char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
phys_size_t ddr_size;
unsigned int lawbar1_target_id;
ulong ddr_freq, ddr_freq_mhz;
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, ddr_freq));
for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
memcpy(&ddr_cfg_regs,
fixed_ddr_parm_0[i].ddr_settings,
sizeof(ddr_cfg_regs));
break;
}
}
if (fixed_ddr_parm_0[i].max_freq == 0)
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, ddr_freq));
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
/*
* setup laws for DDR. If not interleaving, presuming half memory on
* DDR1 and the other half on DDR2
*/
if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size,
LAW_TRGT_IF_DDR_INTRLV) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
} else {
lawbar1_target_id = LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size,
lawbar1_target_id) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
}
return ddr_size;
}
struct board_specific_params {
u32 n_ranks;
u32 datarate_mhz_high;
u32 clk_adjust;
u32 wrlvl_start;
u32 cpo;
u32 write_data_delay;
u32 force_2T;
};
/*
* This table contains all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*/
static const struct board_specific_params udimm[] = {
/*
* memory controller 0
* num| hi| clk| wrlvl | cpo |wrdata|2T
* ranks| mhz|adjst| start | |delay |
*/
{4, 850, 4, 6, 0xff, 2, 0},
{4, 950, 5, 7, 0xff, 2, 0},
{4, 1050, 5, 8, 0xff, 2, 0},
{4, 1250, 5, 10, 0xff, 2, 0},
{4, 1350, 5, 11, 0xff, 2, 0},
{4, 1666, 5, 12, 0xff, 2, 0},
{2, 850, 5, 6, 0xff, 2, 0},
{2, 950, 5, 7, 0xff, 2, 0},
{2, 1250, 4, 6, 0xff, 2, 0},
{2, 1350, 5, 7, 0xff, 2, 0},
{2, 1666, 5, 8, 0xff, 2, 0},
{1, 850, 4, 5, 0xff, 2, 0},
{1, 950, 4, 7, 0xff, 2, 0},
{1, 1666, 4, 8, 0xff, 2, 0},
{}
};
static const struct board_specific_params rdimm[] = {
/*
* memory controller 0
* num| hi| clk| wrlvl | cpo |wrdata|2T
* ranks| mhz|adjst| start | |delay |
*/
{4, 850, 4, 6, 0xff, 2, 0},
{4, 950, 5, 7, 0xff, 2, 0},
{4, 1050, 5, 8, 0xff, 2, 0},
{4, 1250, 5, 10, 0xff, 2, 0},
{4, 1350, 5, 11, 0xff, 2, 0},
{4, 1666, 5, 12, 0xff, 2, 0},
{2, 850, 4, 6, 0xff, 2, 0},
{2, 1050, 4, 7, 0xff, 2, 0},
{2, 1666, 4, 8, 0xff, 2, 0},
{1, 850, 4, 5, 0xff, 2, 0},
{1, 950, 4, 7, 0xff, 2, 0},
{1, 1666, 4, 8, 0xff, 2, 0},
{}
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_params *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
if (ctrl_num) {
printf("Wrong parameter for controller number %d", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
if (popts->registered_dimm_en)
pbsp = rdimm;
else
pbsp = udimm;
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->twoT_en = pbsp->force_2T;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found "
"for data rate %lu MT/s!\n"
"Trying to use the highest speed (%u) parameters\n",
ddr_freq, pbsp_highest->datarate_mhz_high);
popts->cpo_override = pbsp_highest->cpo;
popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->twoT_en = pbsp_highest->force_2T;
} else {
panic("DIMM is not supported by this board");
}
found:
/*
* The datasheet of HMT125U7BFR8C-H9 blocks CL=7 as reservered.
* However SPD still claims CL=7 is supported. Extensive tests
* confirmed this board cannot work stably with CL=7 with this
* particular DIMM.
*/
if (ddr_freq >= 800 && ddr_freq < 1066 && \
!strncmp(pdimm[0].mpart, "HMT125U7BFR8C-H9", 16)) {
popts->cas_latency_override = 1;
popts->cas_latency_override_value = 8;
debug("Override CL to 8\n");
}
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/*
* Rtt and Rtt_WR override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;