Commit 067716ba authored by Tom Rini's avatar Tom Rini

ARM: Move SYS_CACHELINE_SIZE over to Kconfig

This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.  Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: 's avatarLokesh Vutla <lokeshvutla@ti.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefan Agner <stefan.agner@toradex.com>
Acked-by: 's avatarHeiko Schocher <hs@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Acked-by: 's avatarPaul Kocialkowski <contact@paulk.fr>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: 's avatar"Pali Rohár" <pali.rohar@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Alison Wang <b18965@freescale.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Saksham Jain <saksham.jain@nxp.com>
Cc: Qianyu Gong <qianyu.gong@nxp.com>
Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
Cc: tang yuantian <Yuantian.Tang@freescale.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Anand Moon <linux.amoon@gmail.com>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Carlo Caione <carlo@endlessm.com>
Cc: huang lin <hl@rock-chips.com>
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: "Andrew F. Davis" <afd@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Carlos Hernandez <ceh@ti.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: 's avatarTom Rini <trini@konsulko.com>
Acked-by: 's avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: 's avatarChin Liang See <clsee@altera.com>
Tested-by: 's avatarStephen Warren <swarren@nvidia.com>
Acked-by: 's avatarPaul Kocialkowski <contact@paulk.fr>
parent da968c7b
......@@ -7,6 +7,7 @@ config SYS_ARCH
config ARM64
bool
select PHYS_64BIT
select SYS_CACHE_SHIFT_6
config DMA_ADDR_T_64BIT
bool
......@@ -20,37 +21,47 @@ config HAS_THUMB2
config CPU_ARM720T
bool
select SYS_CACHE_SHIFT_5
config CPU_ARM920T
bool
select SYS_CACHE_SHIFT_5
config CPU_ARM926EJS
bool
select SYS_CACHE_SHIFT_5
config CPU_ARM946ES
bool
select SYS_CACHE_SHIFT_5
config CPU_ARM1136
bool
select SYS_CACHE_SHIFT_5
config CPU_ARM1176
bool
select HAS_VBAR
select SYS_CACHE_SHIFT_5
config CPU_V7
bool
select HAS_VBAR
select HAS_THUMB2
select SYS_CACHE_SHIFT_6
config CPU_V7M
bool
select HAS_THUMB2
select SYS_CACHE_SHIFT_5
config CPU_PXA
bool
select SYS_CACHE_SHIFT_5
config CPU_SA1100
bool
select SYS_CACHE_SHIFT_5
config SYS_CPU
default "arm720t" if CPU_ARM720T
......@@ -79,6 +90,21 @@ config SYS_ARM_ARCH
default 4 if CPU_SA1100
default 8 if ARM64
config SYS_CACHE_SHIFT_5
bool
config SYS_CACHE_SHIFT_6
bool
config SYS_CACHE_SHIFT_7
bool
config SYS_CACHELINE_SIZE
int
default 128 if SYS_CACHE_SHIFT_7
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
config SEMIHOSTING
bool "support boot from semihosting"
help
......@@ -867,6 +893,7 @@ config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
select ARM64
select OF_CONTROL
select SYS_CACHE_SHIFT_7
endchoice
......
......@@ -53,11 +53,6 @@ static void cache_flush(void)
}
#ifndef CONFIG_SYS_DCACHE_OFF
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
......
......@@ -8,11 +8,6 @@
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
......
......@@ -8,11 +8,6 @@
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif
void invalidate_dcache_all(void)
{
/* Flush/Invalidate I cache */
......
......@@ -16,8 +16,6 @@
#define _ARMD1_CONFIG_H
#include <asm/arch/armada100.h>
/* default Dcache Line length for armada100 */
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
......
......@@ -36,7 +36,6 @@
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define CONFIG_SYS_CACHELINE_SIZE 64
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
......@@ -150,7 +149,6 @@
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_FSL_LSCH2)
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
......
......@@ -7,8 +7,6 @@
#ifndef _ASM_ARMV7_LS102XA_CONFIG_
#define _ASM_ARMV7_LS102XA_CONFIG_
#define CONFIG_SYS_CACHELINE_SIZE 64
#define OCRAM_BASE_ADDR 0x10000000
#define OCRAM_SIZE 0x00010000
#define OCRAM_BASE_S_ADDR 0x10010000
......
......@@ -9,8 +9,6 @@
#define ARCH_MXC
#define CONFIG_SYS_CACHELINE_SIZE 64
#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
#define IPU_SOC_BASE_ADDR 0x40000000
......
......@@ -9,12 +9,6 @@
#define ARCH_MXC
#ifdef CONFIG_MX6UL
#define CONFIG_SYS_CACHELINE_SIZE 64
#else
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
......
......@@ -9,8 +9,6 @@
#define ARCH_MXC
#define CONFIG_SYS_CACHELINE_SIZE 64
#define ROM_SW_INFO_ADDR 0x000001E8
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x00017FFF
......
......@@ -43,14 +43,11 @@ void dram_bank_mmu_setup(int bank);
#endif
/*
* The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
* use that value for aligning DMA buffers unless the board config has specified
* an alternate cache line size.
* The value of the largest data cache relevant to DMA operations shall be set
* for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger
* value than found in the L1 cache but this is OK to use in terms of
* alignment.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 64
#endif
#endif /* _ASM_CACHE_H */
......@@ -10,10 +10,6 @@
#include <common.h>
#include <malloc.h>
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif
/*
* Flush range from all levels of d-cache/unified-cache.
* Affects the range [start, start + size - 1].
......
......@@ -24,8 +24,6 @@
#endif /* CONFIG_KW88F6281 */
#include <asm/arch/soc.h>
#define CONFIG_SYS_CACHELINE_SIZE 32
/* default Dcache Line length for kirkwood */
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
......
......@@ -26,8 +26,6 @@
#define MV88F78X60 /* for the DDR training bin_hdr code */
#endif
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_L2_PL310
#ifdef CONFIG_SPL_BUILD
......
......@@ -75,6 +75,7 @@ config ARCH_UNIPHIER_LD6B
config CACHE_UNIPHIER
bool "Enable the UniPhier L2 cache controller"
depends on ARCH_UNIPHIER_32BIT
select SYS_CACHE_SHIFT_7
default y
help
This option allows to use the UniPhier System Cache as L2 cache.
......
......@@ -13,8 +13,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* High Level Configuration Options
*/
......
......@@ -18,8 +18,6 @@
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
......
......@@ -11,7 +11,6 @@
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
......@@ -49,7 +48,6 @@
/* Enabling L2 Cache */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x48242000
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* Since SPL did pll and ddr initialization for us,
......
......@@ -12,8 +12,6 @@
#include <asm/hardware.h>
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TEXT_BASE 0x26f00000
/* ARM asynchronous clock */
......
......@@ -127,7 +127,6 @@
/* Commands */
#define CONFIG_FAT_WRITE
#define CONFIG_SYS_CACHELINE_SIZE 64
#undef CONFIG_USB_GADGET_VBUS_DRAW
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#define CONFIG_USBID_ADDR 0x34052c46
......
......@@ -126,7 +126,6 @@
/* Commands */
#define CONFIG_FAT_WRITE
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_USBID_ADDR 0x34052c46
#endif /* __BCM28155_AP_H */
......@@ -11,8 +11,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* Memory configuration
* (these must be defined elsewhere)
......
......@@ -15,7 +15,6 @@
#define CONFIG_AM33XX
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Timer information */
......
......@@ -10,8 +10,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* High Level Configuration Options
*/
......@@ -30,7 +28,6 @@
* Although the default iss 64, we still define it
* to be on the safe side once the default is changed.
*/
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
......
......@@ -79,7 +79,6 @@
/* Enabling L2 Cache */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x48242000
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* Since SPL did pll and ddr initialization for us,
......
......@@ -12,8 +12,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_CACHELINE_SIZE 32
#include <asm/arch/imx-regs.h>
#define CONFIG_VF610
......@@ -207,8 +205,6 @@
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_CACHELINE_SIZE 32
/* USB Host Support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_VF
......
......@@ -118,7 +118,6 @@
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
#define CONFIG_SYS_CACHELINE_SIZE SZ_8K
#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6
/* bootstrap + u-boot + env in nandflash */
......
......@@ -27,8 +27,6 @@
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16MB max kernel size */
#define CONFIG_SYS_CACHELINE_SIZE 64
/* UART */
#define CONFIG_BAUDRATE 115200
......
......@@ -15,7 +15,6 @@
#define CONFIG_BOARD_COMMON
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_REVISION_TAG
/* SD/MMC configuration */
......
......@@ -13,7 +13,6 @@
#include "exynos-common.h"
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_EXYNOS_SPL
#ifdef FTRACE
......
......@@ -19,7 +19,6 @@
#define CONFIG_MX35
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_DISPLAY_CPUINFO
......
......@@ -21,9 +21,6 @@
#define CONFIG_SUPPORT_RAW_INITRD
/* MMU Definitions */
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_IDENT_STRING "hikey"
#define CONFIG_BOARD_EARLY_INIT_F
......
......@@ -24,7 +24,6 @@
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0x48242000
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* Platform
......
......@@ -10,8 +10,6 @@
#undef DEBUG
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SH73A0
#define CONFIG_KZM_A9_GT
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "KMC KZM-A9-GT"
......
......@@ -25,8 +25,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
......
......@@ -10,7 +10,6 @@
#define CONFIG_CPU_ARMV8
#define CONFIG_REMAKE_ELF
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_ENV_IS_NOWHERE 1
......
......@@ -19,8 +19,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* High Level Configuration Options
*/
......
......@@ -275,8 +275,6 @@
#define CONFIG_OMAP3_SPI
#define CONFIG_SYS_CACHELINE_SIZE 64
/* Defines for SPL */
#define CONFIG_SPL_OMAP3_ID_NAND
......
......@@ -192,8 +192,6 @@
#define CONFIG_OMAP3_SPI
#define CONFIG_SYS_CACHELINE_SIZE 64
/* Defines for SPL */
#define CONFIG_SPL_OMAP3_ID_NAND
......
......@@ -340,8 +340,6 @@
/* Uncomment to define the board revision statically */
/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
#define CONFIG_SYS_CACHELINE_SIZE 64
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40200800
......
......@@ -82,7 +82,6 @@
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
#define CONFIG_SYS_CACHELINE_SIZE 64
/* TWL4030 */
#define CONFIG_TWL4030_PWM
......
......@@ -215,7 +215,6 @@
/* Initial RAM setup */
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_CACHELINE_SIZE 64
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
......
......@@ -119,6 +119,4 @@
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
#define CONFIG_SYS_CACHELINE_SIZE 64
#endif /* __CONFIG_H */
......@@ -176,8 +176,6 @@
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
#define CONFIG_SYS_CACHELINE_SIZE 64
#ifdef CONFIG_CMD_NET
/* Ethernet (LAN9211 from SMSC9118 family) */
#define CONFIG_SMC911X
......
......@@ -9,8 +9,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_CACHELINE_SIZE 32
#include <asm/arch/imx-regs.h>
#define CONFIG_VF610
......
......@@ -9,8 +9,6 @@
#ifndef __RCAR_GEN2_COMMON_H
#define __RCAR_GEN2_COMMON_H
#define CONFIG_SYS_CACHELINE_SIZE 64
#include <asm/arch/rmobile.h>
#define CONFIG_CMD_DFL
......
......@@ -6,8 +6,6 @@
#ifndef __CONFIG_RK3036_COMMON_H
#define __CONFIG_RK3036_COMMON_H
#define CONFIG_SYS_CACHELINE_SIZE 64
#include <asm/arch/hardware.h>
#define CONFIG_SYS_NO_FLASH
......
......@@ -7,8 +7,6 @@
#ifndef __CONFIG_RK3288_COMMON_H
#define __CONFIG_RK3288_COMMON_H
#define CONFIG_SYS_CACHELINE_SIZE 64
#include <asm/arch/hardware.h>
#define CONFIG_SYS_NO_FLASH
......
......@@ -7,8 +7,6 @@
#ifndef __CONFIG_RK3399_COMMON_H
#define __CONFIG_RK3399_COMMON_H
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_ENV_SIZE 0x2000
......
......@@ -14,12 +14,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#ifdef CONFIG_BCM2835
#define CONFIG_SYS_CACHELINE_SIZE 32
#else
#define CONFIG_SYS_CACHELINE_SIZE 64
#endif
/* Architecture, CPU, etc.*/
#define CONFIG_ARCH_CPU_INIT
......
......@@ -17,8 +17,6 @@
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
#define CONFIG_MACH_GONI 1 /* working with Goni */
#define CONFIG_SYS_CACHELINE_SIZE 64
#include <linux/sizes.h>
#include <asm/arch/cpu.h> /* get chip and board defs */
......@@ -236,8 +234,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX8998
......
......@@ -36,8 +36,6 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SYS_CACHELINE_SIZE 64
/* commands to include */
#define CONFIG_ENV_VARS_UBOOT_CONFIG
......
......@@ -170,8 +170,6 @@
#define CONFIG_DFU_NAND
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
#define DFU_MANIFEST_POLL_TIMEOUT 25000
#define CONFIG_SYS_CACHELINE_SIZE 0x2000
#endif
/* General Boot Parameter */
......
......@@ -12,8 +12,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* High Level Configuration Options
* (easy to change)
......
......@@ -16,8 +16,6 @@
* CPU
*/
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_ARM_ARCH_CP15_ERRATA
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
......
......@@ -75,7 +75,6 @@
/*
* Cache
*/
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
......
......@@ -55,7 +55,6 @@
/* CPU */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_TIMER_CLK_FREQ 24000000
/*
......
......@@ -23,8 +23,6 @@
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
......
......@@ -13,8 +13,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* High Level Configuration Options
*/
......
......@@ -133,8 +133,6 @@
#define CONFIG_DFU_NAND
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
#define CONFIG_SYS_CACHELINE_SIZE SZ_8K
#endif
/* SPI EEPROM */
......
......@@ -8,9 +8,6 @@
#define _TEGRA114_COMMON_H_
#include "tegra-common.h"
/* Cortex-A15 uses a cache line size of 64 bytes */
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* NS16550 Configuration
*/
......
......@@ -10,9 +10,6 @@
#include "tegra-common.h"
/* Cortex-A15 uses a cache line size of 64 bytes */
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* NS16550 Configuration
*/
......
......@@ -9,9 +9,6 @@
#include "tegra-common.h"
/* Cortex-A57 uses a cache line size of 64 bytes */
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* NS16550 Configuration
*/
......
......@@ -9,9 +9,6 @@
#define _TEGRA20_COMMON_H_