Commit 0c12a159 authored by vijay rai's avatar vijay rai Committed by York Sun

powerpc/85xx: Enhance get_sys_info() to check clocking mode

T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode.

In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock
(100MHz) to the following PLLs:
• Platform PLL
• Core PLLs
• USB PLL
• DDR PLL, etc

The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or
DIFF_SYSCLK (differential) is selected as the clock input to the chip.

get_sys_info has been enhanced to add the diff_sysclk so that the
various drivers can be made aware of ths diff sysclk configuration and
act accordingly.

Other changes:
-single_src to ddr_refclk_sel, as it is use for checking ddr reference clock
-Removed the print of single_src from get_sys_info as this will be
-printed whenever somebody calls get_sys_info which is not appropriate.
-Add print of single_src in checkcpu as it is called only once during initialization
Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: default avatarPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: default avatarVijay Rai <vijay.rai@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
parent b0615f0b
......@@ -130,6 +130,11 @@ int checkcpu (void)
get_sys_info(&sysinfo);
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
if (sysinfo.diff_sysclk == 1)
puts("Single Source Clock Configuration\n");
#endif
puts("Clock Configuration:");
for_each_cpu(i, core, nr_cores, mask) {
if (!(i & 3))
......
......@@ -74,28 +74,33 @@ void get_sys_info(sys_info_t *sys_info)
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
uint mem_pll_rat;
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
uint single_src;
#endif
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
uint ddr_refclk_sel;
unsigned int porsr1_sys_clk;
porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
& FSL_DCFG_PORSR1_SYSCLK_MASK;
if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
sys_info->diff_sysclk = 1;
else
sys_info->diff_sysclk = 0;
/*
* DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
* are driven by separate DDR Refclock or single source
* differential clock.
*/
single_src = (in_be32(&gur->rcwsr[5]) >>
ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
/*
* For single source clocking, both ddrclock and syclock
* For single source clocking, both ddrclock and sysclock
* are driven by differential sysclock.
*/
if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
printf("Single Source Clock Configuration\n");
if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
} else
else
#endif
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
......
......@@ -1583,6 +1583,12 @@ typedef struct cpc_corenet {
typedef struct ccsr_gur {
u32 porsr1; /* POR status 1 */
u32 porsr2; /* POR status 2 */
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15
#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
#endif
u8 res_008[0x20-0x8];
u32 gpporcr1; /* General-purpose POR configuration */
u32 gpporcr2; /* General-purpose POR configuration 2 */
......
......@@ -24,6 +24,9 @@ typedef struct
#ifdef CONFIG_SYS_DPAA_PME
unsigned long freq_pme;
#endif
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
unsigned char diff_sysclk;
#endif
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */
......
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