Commit 0dd38a35 authored by Priyanka Jain's avatar Priyanka Jain Committed by York Sun

powerpc: Fix CamelCase warnings in DDR related code

Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.pl

Convert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.
Signed-off-by: default avatarPriyanka Jain <Priyanka.Jain@freescale.com>
parent 262737f0
......@@ -12,39 +12,39 @@
typedef struct {
/* parameters to constrict */
unsigned int tCKmin_X_ps;
unsigned int tCKmax_ps;
unsigned int tCKmax_max_ps;
unsigned int tRCD_ps;
unsigned int tRP_ps;
unsigned int tRAS_ps;
unsigned int tWR_ps; /* maximum = 63750 ps */
unsigned int tWTR_ps; /* maximum = 63750 ps */
unsigned int tRFC_ps; /* maximum = 255 ns + 256 ns + .75 ns
unsigned int tckmin_x_ps;
unsigned int tckmax_ps;
unsigned int tckmax_max_ps;
unsigned int trcd_ps;
unsigned int trp_ps;
unsigned int tras_ps;
unsigned int twr_ps; /* maximum = 63750 ps */
unsigned int twtr_ps; /* maximum = 63750 ps */
unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns
= 511750 ps */
unsigned int tRRD_ps; /* maximum = 63750 ps */
unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
unsigned int trrd_ps; /* maximum = 63750 ps */
unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
unsigned int refresh_rate_ps;
unsigned int tIS_ps; /* byte 32, spd->ca_setup */
unsigned int tIH_ps; /* byte 33, spd->ca_hold */
unsigned int tDS_ps; /* byte 34, spd->data_setup */
unsigned int tDH_ps; /* byte 35, spd->data_hold */
unsigned int tRTP_ps; /* byte 38, spd->trtp */
unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */
unsigned int tQHS_ps; /* byte 45, spd->tqhs */
unsigned int tis_ps; /* byte 32, spd->ca_setup */
unsigned int tih_ps; /* byte 33, spd->ca_hold */
unsigned int tds_ps; /* byte 34, spd->data_setup */
unsigned int tdh_ps; /* byte 35, spd->data_hold */
unsigned int trtp_ps; /* byte 38, spd->trtp */
unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */
unsigned int tqhs_ps; /* byte 45, spd->tqhs */
unsigned int ndimms_present;
unsigned int lowest_common_SPD_caslat;
unsigned int highest_common_derated_caslat;
unsigned int additive_latency;
unsigned int all_DIMMs_burst_lengths_bitmask;
unsigned int all_DIMMs_registered;
unsigned int all_DIMMs_unbuffered;
unsigned int all_DIMMs_ECC_capable;
unsigned int all_dimms_burst_lengths_bitmask;
unsigned int all_dimms_registered;
unsigned int all_dimms_unbuffered;
unsigned int all_dimms_ecc_capable;
unsigned long long total_mem;
unsigned long long base_address;
......
......@@ -353,14 +353,14 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
/* Control Adjust */
unsigned int cntl_adj = 0;
ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4;
ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4;
ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4;
ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
ext_caslat = (2 * cas_latency - 1) >> 4;
ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) +
(popts->OTF_burst_chop_en ? 2 : 0)) >> 4;
ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
ddr->timing_cfg_3 = (0
| ((ext_pretoact & 0x1) << 28)
......@@ -400,9 +400,9 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
static const u8 wrrec_table[] = {
1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
/*
* Translate CAS Latency to a DDR controller field value:
......@@ -433,17 +433,17 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
caslat_ctrl = 2 * cas_latency - 1;
#endif
refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
if (wrrec_mclk > 16)
printf("Error: WRREC doesn't support more than 16 clocks\n");
else
wrrec_mclk = wrrec_table[wrrec_mclk - 1];
if (popts->OTF_burst_chop_en)
if (popts->otf_burst_chop_en)
wrrec_mclk += 2;
acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
/*
* JEDEC has min requirement for tRRD
*/
......@@ -451,7 +451,7 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
if (acttoact_mclk < 4)
acttoact_mclk = 4;
#endif
wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
/*
* JEDEC has some min requirements for tWTR
*/
......@@ -462,7 +462,7 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
if (wrtord_mclk < 4)
wrtord_mclk = 4;
#endif
if (popts->OTF_burst_chop_en)
if (popts->otf_burst_chop_en)
wrtord_mclk += 2;
ddr->timing_cfg_1 = (0
......@@ -518,7 +518,7 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
wr_lat = compute_cas_write_latency();
#endif
rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
/*
* JEDEC has some min requirements for tRTP
*/
......@@ -531,12 +531,12 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
#endif
if (additive_latency)
rd_to_pre += additive_latency;
if (popts->OTF_burst_chop_en)
if (popts->otf_burst_chop_en)
rd_to_pre += 2; /* according to UM */
wr_data_delay = popts->write_data_delay;
cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
ddr->timing_cfg_2 = (0
| ((add_lat_mclk & 0xf) << 28)
......@@ -555,8 +555,8 @@ static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm)
{
if (common_dimm->all_DIMMs_registered
&& !common_dimm->all_DIMMs_unbuffered) {
if (common_dimm->all_dimms_registered &&
!common_dimm->all_dimms_unbuffered) {
if (popts->rcw_override) {
ddr->ddr_sdram_rcw_1 = popts->rcw_1;
ddr->ddr_sdram_rcw_2 = popts->rcw_2;
......@@ -599,8 +599,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
unsigned int dbw; /* DRAM dta bus width */
unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
unsigned int ncap = 0; /* Non-concurrent auto-precharge */
unsigned int threeT_en; /* Enable 3T timing */
unsigned int twoT_en; /* Enable 2T timing */
unsigned int threet_en; /* Enable 3T timing */
unsigned int twot_en; /* Enable 2T timing */
unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
unsigned int x32_en = 0; /* x32 enable */
unsigned int pchb8 = 0; /* precharge bit 8 enable */
......@@ -610,20 +610,20 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
mem_en = 1;
sren = popts->self_refresh_in_sleep;
if (common_dimm->all_DIMMs_ECC_capable) {
if (common_dimm->all_dimms_ecc_capable) {
/* Allow setting of ECC only if all DIMMs are ECC. */
ecc_en = popts->ECC_mode;
ecc_en = popts->ecc_mode;
} else {
ecc_en = 0;
}
if (common_dimm->all_DIMMs_registered
&& !common_dimm->all_DIMMs_unbuffered) {
if (common_dimm->all_dimms_registered &&
!common_dimm->all_dimms_unbuffered) {
rd_en = 1;
twoT_en = 0;
twot_en = 0;
} else {
rd_en = 0;
twoT_en = popts->twoT_en;
twot_en = popts->twot_en;
}
sdram_type = CONFIG_FSL_SDRAM_TYPE;
......@@ -643,7 +643,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
eight_be = 1;
}
threeT_en = popts->threeT_en;
threet_en = popts->threet_en;
ba_intlv_ctl = popts->ba_intlv_ctl;
hse = popts->half_strength_driver_enable;
......@@ -657,8 +657,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
| ((dbw & 0x3) << 19)
| ((eight_be & 0x1) << 18)
| ((ncap & 0x1) << 17)
| ((threeT_en & 0x1) << 16)
| ((twoT_en & 0x1) << 15)
| ((threet_en & 0x1) << 16)
| ((twot_en & 0x1) << 15)
| ((ba_intlv_ctl & 0x7F) << 8)
| ((x32_en & 0x1) << 5)
| ((pchb8 & 0x1) << 4)
......@@ -691,7 +691,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
int i;
dll_rst_dis = 1; /* Make this configurable */
dqs_cfg = popts->DQS_config;
dqs_cfg = popts->dqs_config;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (popts->cs_local_opts[i].odt_rd_cfg
|| popts->cs_local_opts[i].odt_wr_cfg) {
......@@ -710,7 +710,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
* << DDR_SDRAM_INTERVAL[REFINT]
*/
#if defined(CONFIG_FSL_DDR3)
obc_cfg = popts->OTF_burst_chop_en;
obc_cfg = popts->otf_burst_chop_en;
#else
obc_cfg = 0;
#endif
......@@ -730,7 +730,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Use the DDR controller to auto initialize memory. */
d_init = popts->ECC_init_using_memctl;
d_init = popts->ecc_init_using_memctl;
ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
#else
......@@ -939,7 +939,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
*/
dll_on = 1;
wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps;
if (wr_mclk <= 16) {
wr = wr_table[wr_mclk - 5];
} else {
......@@ -1101,7 +1101,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
#if defined(CONFIG_FSL_DDR2)
const unsigned int mclk_ps = get_memory_clk_period_ps();
#endif
dqs_en = !popts->DQS_config;
dqs_en = !popts->dqs_config;
rtt = fsl_ddr_get_rtt();
al = additive_latency;
......@@ -1130,7 +1130,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
#if defined(CONFIG_FSL_DDR1)
wr = 0; /* Historical */
#elif defined(CONFIG_FSL_DDR2)
wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1;
#endif
dll_res = 0;
mode = 0;
......
......@@ -72,7 +72,7 @@ unsigned int compute_lowest_common_dimm_parameters(
const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
unsigned int number_of_dimms);
unsigned int populate_memctl_options(int all_DIMMs_registered,
unsigned int populate_memctl_options(int all_dimms_registered,
memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num);
......
......@@ -287,57 +287,57 @@ ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd,
* The SPD clk_cycle field (tCKmin) is measured in tenths of
* nanoseconds and represented as BCD.
*/
pdimm->tCKmin_X_ps
pdimm->tckmin_x_ps
= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
pdimm->tCKmin_X_minus_1_ps
pdimm->tckmin_x_minus_1_ps
= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
pdimm->tCKmin_X_minus_2_ps
pdimm->tckmin_x_minus_2_ps
= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
pdimm->tCKmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
/*
* Compute CAS latencies defined by SPD
* The SPD caslat_X should have at least 1 and at most 3 bits set.
* The SPD caslat_x should have at least 1 and at most 3 bits set.
*
* If cas_lat after masking is 0, the __ilog2 function returns
* 255 into the variable. This behavior is abused once.
*/
pdimm->caslat_X = __ilog2(spd->cas_lat);
pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat
& ~(1 << pdimm->caslat_X));
pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat
& ~(1 << pdimm->caslat_X)
& ~(1 << pdimm->caslat_X_minus_1));
pdimm->caslat_x = __ilog2(spd->cas_lat);
pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
& ~(1 << pdimm->caslat_x));
pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
& ~(1 << pdimm->caslat_x)
& ~(1 << pdimm->caslat_x_minus_1));
/* Compute CAS latencies below that defined by SPD */
pdimm->caslat_lowest_derated
= compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps());
/* Compute timing parameters */
pdimm->tRCD_ps = spd->trcd * 250;
pdimm->tRP_ps = spd->trp * 250;
pdimm->tRAS_ps = spd->tras * 1000;
pdimm->trcd_ps = spd->trcd * 250;
pdimm->trp_ps = spd->trp * 250;
pdimm->tras_ps = spd->tras * 1000;
pdimm->tWR_ps = mclk_to_picos(3);
pdimm->tWTR_ps = mclk_to_picos(1);
pdimm->tRFC_ps = compute_trfc_ps_from_spd(0, spd->trfc);
pdimm->twr_ps = mclk_to_picos(3);
pdimm->twtr_ps = mclk_to_picos(1);
pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
pdimm->tRRD_ps = spd->trrd * 250;
pdimm->tRC_ps = compute_trc_ps_from_spd(0, spd->trc);
pdimm->trrd_ps = spd->trrd * 250;
pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc);
pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
pdimm->tDS_ps
pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
pdimm->tds_ps
= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
pdimm->tDH_ps
pdimm->tdh_ps
= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
pdimm->tRTP_ps = mclk_to_picos(2); /* By the book. */
pdimm->tDQSQ_max_ps = spd->tdqsq * 10;
pdimm->tQHS_ps = spd->tqhs * 10;
pdimm->trtp_ps = mclk_to_picos(2); /* By the book. */
pdimm->tdqsq_max_ps = spd->tdqsq * 10;
pdimm->tqhs_ps = spd->tqhs * 10;
return 0;
}
......@@ -286,57 +286,57 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
* The SPD clk_cycle field (tCKmin) is measured in tenths of
* nanoseconds and represented as BCD.
*/
pdimm->tCKmin_X_ps
pdimm->tckmin_x_ps
= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
pdimm->tCKmin_X_minus_1_ps
pdimm->tckmin_x_minus_1_ps
= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
pdimm->tCKmin_X_minus_2_ps
pdimm->tckmin_x_minus_2_ps
= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
pdimm->tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);
pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);
/*
* Compute CAS latencies defined by SPD
* The SPD caslat_X should have at least 1 and at most 3 bits set.
* The SPD caslat_x should have at least 1 and at most 3 bits set.
*
* If cas_lat after masking is 0, the __ilog2 function returns
* 255 into the variable. This behavior is abused once.
*/
pdimm->caslat_X = __ilog2(spd->cas_lat);
pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat
& ~(1 << pdimm->caslat_X));
pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat
& ~(1 << pdimm->caslat_X)
& ~(1 << pdimm->caslat_X_minus_1));
pdimm->caslat_x = __ilog2(spd->cas_lat);
pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
& ~(1 << pdimm->caslat_x));
pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
& ~(1 << pdimm->caslat_x)
& ~(1 << pdimm->caslat_x_minus_1));
/* Compute CAS latencies below that defined by SPD */
pdimm->caslat_lowest_derated
= compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());
/* Compute timing parameters */
pdimm->tRCD_ps = spd->trcd * 250;
pdimm->tRP_ps = spd->trp * 250;
pdimm->tRAS_ps = spd->tras * 1000;
pdimm->trcd_ps = spd->trcd * 250;
pdimm->trp_ps = spd->trp * 250;
pdimm->tras_ps = spd->tras * 1000;
pdimm->tWR_ps = spd->twr * 250;
pdimm->tWTR_ps = spd->twtr * 250;
pdimm->tRFC_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);
pdimm->twr_ps = spd->twr * 250;
pdimm->twtr_ps = spd->twtr * 250;
pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);
pdimm->tRRD_ps = spd->trrd * 250;
pdimm->tRC_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);
pdimm->trrd_ps = spd->trrd * 250;
pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);
pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
pdimm->tDS_ps
pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
pdimm->tds_ps
= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
pdimm->tDH_ps
pdimm->tdh_ps
= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
pdimm->tRTP_ps = spd->trtp * 250;
pdimm->tDQSQ_max_ps = spd->tdqsq * 10;
pdimm->tQHS_ps = spd->tqhs * 10;
pdimm->trtp_ps = spd->trtp * 250;
pdimm->tdqsq_max_ps = spd->tdqsq * 10;
pdimm->tqhs_ps = spd->tqhs * 10;
return 0;
}
......@@ -210,12 +210,12 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
* sdram minimum cycle time
* we assume the MTB is 0.125ns
* eg:
* tCK_min=15 MTB (1.875ns) ->DDR3-1066
* tck_min=15 MTB (1.875ns) ->DDR3-1066
* =12 MTB (1.5ns) ->DDR3-1333
* =10 MTB (1.25ns) ->DDR3-1600
*/
pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps +
(spd->fine_tCK_min * ftb_10th_ps) / 10;
pdimm->tckmin_x_ps = spd->tck_min * mtb_ps +
(spd->fine_tck_min * ftb_10th_ps) / 10;
/*
* CAS latency supported
......@@ -223,55 +223,55 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
* bit5 - CL5
* bit18 - CL18
*/
pdimm->caslat_X = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
pdimm->caslat_x = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
/*
* min CAS latency time
* eg: tAA_min =
* eg: taa_min =
* DDR3-800D 100 MTB (12.5ns)
* DDR3-1066F 105 MTB (13.125ns)
* DDR3-1333H 108 MTB (13.5ns)
* DDR3-1600H 90 MTB (11.25ns)
*/
pdimm->tAA_ps = spd->tAA_min * mtb_ps +
(spd->fine_tAA_min * ftb_10th_ps) / 10;
pdimm->taa_ps = spd->taa_min * mtb_ps +
(spd->fine_taa_min * ftb_10th_ps) / 10;
/*
* min write recovery time
* eg:
* tWR_min = 120 MTB (15ns) -> all speed grades.
* twr_min = 120 MTB (15ns) -> all speed grades.
*/
pdimm->tWR_ps = spd->tWR_min * mtb_ps;
pdimm->twr_ps = spd->twr_min * mtb_ps;
/*
* min RAS to CAS delay time
* eg: tRCD_min =
* eg: trcd_min =
* DDR3-800 100 MTB (12.5ns)
* DDR3-1066F 105 MTB (13.125ns)
* DDR3-1333H 108 MTB (13.5ns)
* DDR3-1600H 90 MTB (11.25)
*/
pdimm->tRCD_ps = spd->tRCD_min * mtb_ps +
(spd->fine_tRCD_min * ftb_10th_ps) / 10;
pdimm->trcd_ps = spd->trcd_min * mtb_ps +
(spd->fine_trcd_min * ftb_10th_ps) / 10;
/*
* min row active to row active delay time
* eg: tRRD_min =
* eg: trrd_min =
* DDR3-800(1KB page) 80 MTB (10ns)
* DDR3-1333(1KB page) 48 MTB (6ns)
*/
pdimm->tRRD_ps = spd->tRRD_min * mtb_ps;
pdimm->trrd_ps = spd->trrd_min * mtb_ps;
/*
* min row precharge delay time
* eg: tRP_min =
* eg: trp_min =
* DDR3-800D 100 MTB (12.5ns)
* DDR3-1066F 105 MTB (13.125ns)
* DDR3-1333H 108 MTB (13.5ns)
* DDR3-1600H 90 MTB (11.25ns)
*/
pdimm->tRP_ps = spd->tRP_min * mtb_ps +
(spd->fine_tRP_min * ftb_10th_ps) / 10;
pdimm->trp_ps = spd->trp_min * mtb_ps +
(spd->fine_trp_min * ftb_10th_ps) / 10;
/* min active to precharge delay time
* eg: tRAS_min =
......@@ -280,7 +280,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
* DDR3-1333H 288 MTB (36ns)
* DDR3-1600H 280 MTB (35ns)
*/
pdimm->tRAS_ps = (((spd->tRAS_tRC_ext & 0xf) << 8) | spd->tRAS_min_lsb)
pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb)
* mtb_ps;
/*
* min active to actice/refresh delay time
......@@ -290,8 +290,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
* DDR3-1333H 396 MTB (49.5ns)
* DDR3-1600H 370 MTB (46.25ns)
*/
pdimm->tRC_ps = (((spd->tRAS_tRC_ext & 0xf0) << 4) | spd->tRC_min_lsb)
* mtb_ps + (spd->fine_tRC_min * ftb_10th_ps) / 10;
pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb)
* mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10;
/*
* min refresh recovery delay time
* eg: tRFC_min =
......@@ -299,21 +299,21 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
* 1Gb 880 MTB (110ns)
* 2Gb 1280 MTB (160ns)
*/
pdimm->tRFC_ps = ((spd->tRFC_min_msb << 8) | spd->tRFC_min_lsb)
pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb)
* mtb_ps;
/*
* min internal write to read command delay time
* eg: tWTR_min = 40 MTB (7.5ns) - all speed bins.
* eg: twtr_min = 40 MTB (7.5ns) - all speed bins.
* tWRT is at least 4 mclk independent of operating freq.
*/
pdimm->tWTR_ps = spd->tWTR_min * mtb_ps;
pdimm->twtr_ps = spd->twtr_min * mtb_ps;
/*
* min internal read to precharge command delay time
* eg: tRTP_min = 40 MTB (7.5ns) - all speed bins.
* eg: trtp_min = 40 MTB (7.5ns) - all speed bins.
* tRTP is at least 4 mclk independent of operating freq.
*/
pdimm->tRTP_ps = spd->tRTP_min * mtb_ps;
pdimm->trtp_ps = spd->trtp_min * mtb_ps;
/*
* Average periodic refresh interval
......@@ -324,13 +324,13 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
/*
* min four active window delay time
* eg: tFAW_min =
* eg: tfaw_min =
* DDR3-800(1KB page) 320 MTB (40ns)
* DDR3-1066(1KB page) 300 MTB (37.5ns)
* DDR3-1333(1KB page) 240 MTB (30ns)
* DDR3-1600(1KB page) 240 MTB (30ns)
*/
pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min)
pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min)
* mtb_ps;
return 0;
......
This diff is collapsed.
......@@ -457,7 +457,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
* which is currently STEP_ASSIGN_ADDRESSES.
*/
populate_memctl_options(
timing_params[i].all_DIMMs_registered,
timing_params[i].all_dimms_registered,
&pinfo->memctl_opts[i],
pinfo->dimm_params[i], i);
/*
......@@ -466,7 +466,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
* using fixed parameters, this function should be
* be called from board init file.
*/
if (timing_params[i].all_DIMMs_registered)
if (timing_params[i].all_dimms_registered)
assert_reset = 1;
}
if (assert_reset) {
......@@ -589,7 +589,7 @@ phys_size_t fsl_ddr_sdram(void)
*/
deassert_reset = board_need_mem_reset();
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
if (info.common_timing_params[i].all_DIMMs_registered)
if (info.common_timing_params[i].all_dimms_registered)
deassert_reset = 1;
}
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
......
......@@ -499,7 +499,7 @@ static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
return 0;
}
unsigned int populate_memctl_options(int all_DIMMs_registered,
unsigned int populate_memctl_options(int all_dimms_registered,
memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
......@@ -635,20 +635,20 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
popts->ba_intlv_ctl = 0;
/* Memory Organization Parameters */
popts->registered_dimm_en = all_DIMMs_registered;
popts->registered_dimm_en = all_dimms_registered;
/* Operational Mode Paramters */
/* Pick ECC modes */
popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */
#ifdef CONFIG_DDR_ECC
if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
popts->ECC_mode = 1;
popts->ecc_mode = 1;
} else
popts->ECC_mode = 1;
popts->ecc_mode = 1;
#endif
popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
/*
* Choose DQS config
......@@ -656,9 +656,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
* 1 for DDR2
*/
#if defined(CONFIG_FSL_DDR1)
popts->DQS_config = 0;
popts->dqs_config = 0;
#elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
popts->DQS_config = 1;
popts->dqs_config = 1;
#endif
/* Choose self-refresh during sleep. */
......@@ -705,15 +705,15 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
/* Choose burst length. */
#if defined(CONFIG_FSL_DDR3)
#if defined(CONFIG_E500MC)
popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
#else
if ((popts