Commit 0f3d80e9 authored by York Sun's avatar York Sun

powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081

Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead.
Signed-off-by: default avatarYork Sun <york.sun@nxp.com>
parent 01671e66
......@@ -244,16 +244,19 @@ config TARGET_T1042RDB_PI
config TARGET_T2080QDS
bool "Support T2080QDS"
select ARCH_T2080
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_T2080RDB
bool "Support T2080RDB"
select ARCH_T2080
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_T2081QDS
bool "Support T2081QDS"
select ARCH_T2081
select SUPPORT_SPL
select PHYS_64BIT
......@@ -400,6 +403,12 @@ config ARCH_T1040
config ARCH_T1042
bool
config ARCH_T2080
bool
config ARCH_T2081
bool
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
......
......@@ -55,8 +55,8 @@ obj-$(CONFIG_PPC_T1020) += t1040_ids.o
obj-$(CONFIG_PPC_T1022) += t1040_ids.o
obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
obj-$(CONFIG_PPC_T2080) += t2080_ids.o
obj-$(CONFIG_PPC_T2081) += t2080_ids.o
obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
obj-$(CONFIG_ARCH_T2081) += t2080_ids.o
obj-$(CONFIG_QE) += qe_io.o
......@@ -98,8 +98,8 @@ obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
obj-$(CONFIG_PPC_T2081) += t2080_serdes.o
obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
obj-$(CONFIG_ARCH_T2081) += t2080_serdes.o
obj-y += cpu.o
obj-y += cpu_init.o
......
......@@ -511,7 +511,7 @@ static void fdt_fixup_usb(void *fdt)
#define fdt_fixup_usb(x)
#endif
#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \
#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_PPC_T4240) || \
defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
void fdt_fixup_dma3(void *blob)
{
......@@ -520,7 +520,7 @@ void fdt_fixup_dma3(void *blob)
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
#if defined(CONFIG_PPC_T2080)
#if defined(CONFIG_ARCH_T2080)
u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
......
......@@ -131,8 +131,8 @@ void get_sys_info(sys_info_t *sys_info)
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
*/
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \
defined(CONFIG_PPC_T2081)
defined(CONFIG_PPC_T4080) || defined(CONFIG_ARCH_T2080) || \
defined(CONFIG_ARCH_T2081)
svr = get_svr();
switch (SVR_SOC_VER(svr)) {
case SVR_T4240:
......@@ -203,7 +203,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
......@@ -456,7 +456,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
#if defined(CONFIG_PPC_T2080)
#if defined(CONFIG_ARCH_T2080)
#define ESDHC_CLK_SEL 0x00000007
#define ESDHC_CLK_SHIFT 0
#define ESDHC_CLK_RCWSR 15
......@@ -480,7 +480,7 @@ void get_sys_info(sys_info_t *sys_info)
case 4:
sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
break;
#if defined(CONFIG_PPC_T2080)
#if defined(CONFIG_ARCH_T2080)
case 5:
sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
break;
......
......@@ -161,7 +161,7 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
{}
};
#ifndef CONFIG_PPC_T2081
#ifndef CONFIG_ARCH_T2081
static const struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
......@@ -181,7 +181,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
static const struct serdes_config *serdes_cfg_tbl[] = {
serdes1_cfg_tbl,
#ifndef CONFIG_PPC_T2081
#ifndef CONFIG_ARCH_T2081
serdes2_cfg_tbl,
#endif
};
......
......@@ -779,7 +779,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_ERRATUM_A008378
#define CONFIG_SYS_FSL_ERRATUM_A009663
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define CONFIG_E6500
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
......@@ -794,7 +794,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_PCI_VER_3_X
#if defined(CONFIG_PPC_T2080)
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 4
#define CONFIG_SYS_FSL_SRDS_2
......@@ -802,7 +802,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_T2081)
#elif defined(CONFIG_ARCH_T2081)
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#endif
......
......@@ -1812,7 +1812,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
......@@ -1885,7 +1885,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
#endif
#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
......
......@@ -12,7 +12,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
......
......@@ -12,7 +12,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
......
......@@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
......
......@@ -13,7 +13,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
......
......@@ -5,7 +5,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
......
......@@ -5,7 +5,6 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
......
......@@ -12,7 +12,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
......
......@@ -12,7 +12,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
......
......@@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
......
......@@ -13,7 +13,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
......
......@@ -5,7 +5,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
......
......@@ -5,7 +5,6 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
......
......@@ -12,7 +12,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
......
......@@ -12,7 +12,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
......
......@@ -13,7 +13,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
......
......@@ -5,7 +5,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
......
......@@ -5,7 +5,6 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
......
......@@ -30,8 +30,8 @@ obj-$(CONFIG_PPC_T1020) += t1040.o
obj-$(CONFIG_PPC_T1022) += t1040.o
obj-$(CONFIG_ARCH_T1023) += t1024.o
obj-$(CONFIG_ARCH_T1024) += t1024.o
obj-$(CONFIG_PPC_T2080) += t2080.o
obj-$(CONFIG_PPC_T2081) += t2080.o
obj-$(CONFIG_ARCH_T2080) += t2080.o
obj-$(CONFIG_ARCH_T2081) += t2080.o
obj-$(CONFIG_PPC_T4240) += t4240.o
obj-$(CONFIG_PPC_T4160) += t4240.o
obj-$(CONFIG_PPC_T4080) += t4240.o
......
......@@ -14,13 +14,13 @@
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_MMC
#define CONFIG_USB_EHCI
#if defined(CONFIG_PPC_T2080)
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_T2080QDS
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
#elif defined(CONFIG_PPC_T2081)
#elif defined(CONFIG_ARCH_T2081)
#define CONFIG_T2081QDS
#endif
......@@ -69,9 +69,9 @@
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#if defined(CONFIG_PPC_T2080)
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
#elif defined(CONFIG_PPC_T2081)
#elif defined(CONFIG_ARCH_T2081)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
#endif
#define CONFIG_SPL_NAND_BOOT
......@@ -88,9 +88,9 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#if defined(CONFIG_PPC_T2080)
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
#elif defined(CONFIG_PPC_T2081)
#elif defined(CONFIG_ARCH_T2081)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
#endif
#define CONFIG_SPL_SPI_BOOT
......@@ -107,9 +107,9 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#if defined(CONFIG_PPC_T2080)
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
#elif defined(CONFIG_PPC_T2081)
#elif defined(CONFIG_ARCH_T2081)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
#endif
#define CONFIG_SPL_MMC_BOOT
......
......@@ -3640,8 +3640,6 @@ CONFIG_PPC4xx_EMAC
CONFIG_PPC64BRIDGE
CONFIG_PPC_CLUSTER_START
CONFIG_PPC_SPINTABLE_COMPATIBLE
CONFIG_PPC_T2080
CONFIG_PPC_T2081
CONFIG_PPC_T4160
CONFIG_PPC_T4240
CONFIG_PQ_MDS_PIB
......
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