Commit 135aa950 authored by Stephen Warren's avatar Stephen Warren Committed by Simon Glass

clk: convert API to match reset/mailbox style

The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
  provider now implements a single set of clocks. This provides a simpler
  conceptual interface to clients, and better aligns with device tree
  clock bindings.
* Clocks are now identified with a single "struct clk", rather than
  requiring clients to store the clock provider device and clock identity
  values separately. For simple clock consumers, this isolates clients
  from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
  clk-uclass.h contains the provider API. This aligns with the recently
  added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
  can customize these operations if needed. This also aligns with the
  recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
  clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst
others).
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Acked-by: default avatarSimon Glass <sjg@chromium.org>
parent 4581b717
......@@ -62,18 +62,6 @@ static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
*/
void *rockchip_get_cru(void);
/**
* rkclk_get_clk() - get a pointer to a given clock
*
* This is an internal function - use outside the clock subsystem indicates
* that work is needed!
*
* @clk_id: Clock requested
* @devp: Returns a pointer to that clock
* @return 0 if OK, -ve on error
*/
int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp);
struct rk3288_cru;
struct rk3288_grf;
......
......@@ -9,6 +9,7 @@
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -54,15 +55,43 @@ void lowlevel_init(void)
static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
static const struct {
char *name;
int id;
} clks[] = {
{ "osc", CLK_OSC },
{ "apll", CLK_ARM },
{ "dpll", CLK_DDR },
{ "cpll", CLK_CODEC },
{ "gpll", CLK_GENERAL },
#ifdef CONFIG_ROCKCHIP_RK3036
{ "mpll", CLK_NEW },
#else
{ "npll", CLK_NEW },
#endif
};
int ret, i;
struct udevice *dev;
for (uclass_first_device(UCLASS_CLK, &dev);
dev;
uclass_next_device(&dev)) {
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
printf("clk-uclass not found\n");
return 0;
}
for (i = 0; i < ARRAY_SIZE(clks); i++) {
struct clk clk;
ulong rate;
rate = clk_get_rate(dev);
printf("%s: %lu\n", dev->name, rate);
clk.id = clks[i].id;
ret = clk_request(dev, &clk);
if (ret < 0)
continue;
rate = clk_get_rate(&clk);
printf("%s: %lu\n", clks[i].name, rate);
clk_free(&clk);
}
return 0;
......
......@@ -36,7 +36,7 @@ struct chan_info {
struct dram_info {
struct chan_info chan[2];
struct ram_info info;
struct udevice *ddr_clk;
struct clk ddr_clk;
struct rk3288_cru *cru;
struct rk3288_grf *grf;
struct rk3288_sgrf *sgrf;
......@@ -576,7 +576,7 @@ static void dram_all_config(const struct dram_info *dram,
rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
}
static int sdram_init(const struct dram_info *dram,
static int sdram_init(struct dram_info *dram,
const struct rk3288_sdram_params *sdram_params)
{
int channel;
......@@ -592,8 +592,8 @@ static int sdram_init(const struct dram_info *dram,
return -E2BIG;
}
debug("ddr clk %s\n", dram->ddr_clk->name);
ret = clk_set_rate(dram->ddr_clk, sdram_params->base.ddr_freq);
debug("ddr clk dpll\n");
ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
debug("ret=%d\n", ret);
if (ret) {
debug("Could not set DDR clock\n");
......@@ -836,6 +836,7 @@ static int rk3288_dmc_probe(struct udevice *dev)
struct dram_info *priv = dev_get_priv(dev);
struct regmap *map;
int ret;
struct udevice *dev_clk;
map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
if (IS_ERR(map))
......@@ -856,7 +857,11 @@ static int rk3288_dmc_probe(struct udevice *dev)
priv->chan[1].pctl = regmap_get_range(map, 2);
priv->chan[1].publ = regmap_get_range(map, 3);
ret = uclass_get_device(UCLASS_CLK, CLK_DDR, &priv->ddr_clk);
ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk);
if (ret)
return ret;
priv->ddr_clk.id = CLK_DDR;
ret = clk_request(dev_clk, &priv->ddr_clk);
if (ret)
return ret;
......
......@@ -9,7 +9,7 @@
*/
#include <common.h>
#include <clk.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <asm/io.h>
......@@ -212,11 +212,11 @@ static int clk_init_uart(struct msm_clk_priv *priv)
return 0;
}
ulong msm_set_periph_rate(struct udevice *dev, int periph, ulong rate)
ulong msm_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(dev);
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (periph) {
switch (clk->id) {
case 0: /* SDC1 */
return clk_init_sdc(priv, 0, rate);
break;
......@@ -243,7 +243,7 @@ static int msm_clk_probe(struct udevice *dev)
}
static struct clk_ops msm_clk_ops = {
.set_periph_rate = msm_set_periph_rate,
.set_rate = msm_set_rate,
};
static const struct udevice_id msm_clk_ids[] = {
......
......@@ -6,7 +6,6 @@
*/
#include <common.h>
#include <errno.h>
#include <clk.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
......
......@@ -23,18 +23,34 @@
DECLARE_GLOBAL_DATA_PTR;
static ulong clk_get_cpu_rate(void)
static ulong rate(int id)
{
int ret;
struct udevice *dev;
struct clk clk;
ulong rate;
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
panic("uclass-clk: device not found\n");
printf("clk-uclass not found\n");
return 0;
}
return clk_get_rate(dev);
clk.id = id;
ret = clk_request(dev, &clk);
if (ret < 0)
return ret;
rate = clk_get_rate(&clk);
clk_free(&clk);
return rate;
}
static ulong clk_get_cpu_rate(void)
{
return rate(PB7CLK);
}
/* initialize prefetch module related to cpu_clk */
......@@ -127,30 +143,25 @@ const char *get_core_name(void)
}
#endif
#ifdef CONFIG_CMD_CLK
int soc_clk_dump(void)
{
int i, ret;
struct udevice *dev;
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
printf("clk-uclass not found\n");
return ret;
}
int i;
printf("PLL Speed: %lu MHz\n",
CLK_MHZ(clk_get_periph_rate(dev, PLLCLK)));
printf("CPU Speed: %lu MHz\n", CLK_MHZ(clk_get_rate(dev)));
printf("MPLL Speed: %lu MHz\n",
CLK_MHZ(clk_get_periph_rate(dev, MPLL)));
CLK_MHZ(rate(PLLCLK)));
printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
for (i = PB1CLK; i <= PB7CLK; i++)
printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
CLK_MHZ(clk_get_periph_rate(dev, i)));
CLK_MHZ(rate(i)));
for (i = REF1CLK; i <= REF5CLK; i++)
printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
CLK_MHZ(clk_get_periph_rate(dev, i)));
CLK_MHZ(rate(i)));
return 0;
}
#endif
......@@ -108,8 +108,23 @@
compatible = "denx,u-boot-fdt-test";
};
clk@0 {
clk_fixed: clk-fixed {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1234>;
};
clk_sandbox: clk-sbox {
compatible = "sandbox,clk";
#clock-cells = <1>;
};
clk-test {
compatible = "sandbox,clk-test";
clocks = <&clk_fixed>,
<&clk_sandbox 1>,
<&clk_sandbox 0>;
clock-names = "fixed", "i2c", "spi";
};
eth@10002000 {
......
/*
* Copyright (c) 2016, NVIDIA CORPORATION.
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __SANDBOX_CLK_H
#define __SANDBOX_CLK_H
#include <common.h>
struct udevice;
/**
* enum sandbox_clk_id - Identity of clocks implemented by the sandbox clock
* provider.
*
* These IDs are within/relative-to the clock provider.
*/
enum sandbox_clk_id {
SANDBOX_CLK_ID_SPI,
SANDBOX_CLK_ID_I2C,
SANDBOX_CLK_ID_COUNT,
};
/**
* enum sandbox_clk_test_id - Identity of the clocks consumed by the sandbox
* clock test device.
*
* These are the IDs the clock consumer knows the clocks as.
*/
enum sandbox_clk_test_id {
SANDBOX_CLK_TEST_ID_FIXED,
SANDBOX_CLK_TEST_ID_SPI,
SANDBOX_CLK_TEST_ID_I2C,
SANDBOX_CLK_TEST_ID_COUNT,
};
/**
* sandbox_clk_query_rate - Query the current rate of a sandbox clock.
*
* @dev: The sandbox clock provider device.
* @id: The clock to query.
* @return: The rate of the clock.
*/
ulong sandbox_clk_query_rate(struct udevice *dev, int id);
/**
* sandbox_clk_query_enable - Query the enable state of a sandbox clock.
*
* @dev: The sandbox clock provider device.
* @id: The clock to query.
* @return: The rate of the clock.
*/
int sandbox_clk_query_enable(struct udevice *dev, int id);
/**
* sandbox_clk_test_get - Ask the sandbox clock test device to request its
* clocks.
*
* @dev: The sandbox clock test (client) devivce.
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_get(struct udevice *dev);
/**
* sandbox_clk_test_get_rate - Ask the sandbox clock test device to query a
* clock's rate.
*
* @dev: The sandbox clock test (client) devivce.
* @id: The test device's clock ID to query.
* @return: The rate of the clock.
*/
ulong sandbox_clk_test_get_rate(struct udevice *dev, int id);
/**
* sandbox_clk_test_set_rate - Ask the sandbox clock test device to set a
* clock's rate.
*
* @dev: The sandbox clock test (client) devivce.
* @id: The test device's clock ID to configure.
* @return: The new rate of the clock.
*/
ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate);
/**
* sandbox_clk_test_enable - Ask the sandbox clock test device to enable a
* clock.
*
* @dev: The sandbox clock test (client) devivce.
* @id: The test device's clock ID to configure.
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_enable(struct udevice *dev, int id);
/**
* sandbox_clk_test_disable - Ask the sandbox clock test device to disable a
* clock.
*
* @dev: The sandbox clock test (client) devivce.
* @id: The test device's clock ID to configure.
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_disable(struct udevice *dev, int id);
/**
* sandbox_clk_test_free - Ask the sandbox clock test device to free its
* clocks.
*
* @dev: The sandbox clock test (client) devivce.
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_free(struct udevice *dev);
#endif
......@@ -19,15 +19,6 @@
#define SANDBOX_CLK_RATE 32768
enum {
PERIPH_ID_FIRST = 0,
PERIPH_ID_SPI = PERIPH_ID_FIRST,
PERIPH_ID_I2C,
PERIPH_ID_PCI,
PERIPH_ID_COUNT,
};
/* System controller driver data */
enum {
SYSCON0 = 32,
......
......@@ -11,20 +11,31 @@
#include <common.h>
#include <dm.h>
#include <clk.h>
#include <dt-bindings/clock/microchip,clock.h>
#include <mach/pic32.h>
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
ulong rate = 0;
ulong rate;
struct udevice *dev;
struct clk clk;
int ret;
printf("Core: %s\n", get_core_name());
if (!uclass_get_device(UCLASS_CLK, 0, &dev)) {
rate = clk_get_rate(dev);
printf("CPU Speed: %lu MHz\n", rate / 1000000);
}
if (uclass_get_device(UCLASS_CLK, 0, &dev))
return 0;
clk.id = PB7CLK;
ret = clk_request(dev, &clk);
if (ret < 0)
return 0;
rate = clk_get_rate(&clk);
printf("CPU Speed: %lu MHz\n", rate / 1000000);
clk_free(&clk);
return 0;
}
......
......@@ -9,6 +9,7 @@ obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o
obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_EXYNOS) += exynos/
/*
* Copyright (C) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
* Copyright (c) 2016, NVIDIA CORPORATION.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <dm/lists.h>
#include <dm/root.h>
DECLARE_GLOBAL_DATA_PTR;
ulong clk_get_rate(struct udevice *dev)
static inline struct clk_ops *clk_dev_ops(struct udevice *dev)
{
struct clk_ops *ops = clk_get_ops(dev);
if (!ops->get_rate)
return -ENOSYS;
return ops->get_rate(dev);
return (struct clk_ops *)dev->driver->ops;
}
ulong clk_set_rate(struct udevice *dev, ulong rate)
#if CONFIG_IS_ENABLED(OF_CONTROL)
#ifdef CONFIG_SPL_BUILD
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
{
struct clk_ops *ops = clk_get_ops(dev);
int ret;
u32 cell[2];
if (!ops->set_rate)
if (index != 0)
return -ENOSYS;
return ops->set_rate(dev, rate);
assert(clk);
ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
if (ret)
return ret;
ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clocks",
cell, 2);
if (ret)
return ret;
clk->id = cell[1];
return 0;
}
int clk_enable(struct udevice *dev, int periph)
int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
{
struct clk_ops *ops = clk_get_ops(dev);
if (!ops->enable)
return -ENOSYS;
return ops->enable(dev, periph);
return -ENOSYS;
}
ulong clk_get_periph_rate(struct udevice *dev, int periph)
#else
static int clk_of_xlate_default(struct clk *clk,
struct fdtdec_phandle_args *args)
{
struct clk_ops *ops = clk_get_ops(dev);
debug("%s(clk=%p)\n", __func__, clk);
if (!ops->get_periph_rate)
return -ENOSYS;
return ops->get_periph_rate(dev, periph);
}
ulong clk_set_periph_rate(struct udevice *dev, int periph, ulong rate)
{
struct clk_ops *ops = clk_get_ops(dev);
if (args->args_count > 1) {
debug("Invaild args_count: %d\n", args->args_count);
return -EINVAL;
}
if (!ops->set_periph_rate)
return -ENOSYS;
if (args->args_count)
clk->id = args->args[0];
else
clk->id = 0;
return ops->set_periph_rate(dev, periph, rate);
return 0;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
int clk_get_by_index(struct udevice *dev, int index, struct udevice **clk_devp)
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
{
int ret;
#ifdef CONFIG_SPL_BUILD
u32 cell[2];
if (index != 0)
return -ENOSYS;
assert(*clk_devp);
ret = uclass_get_device(UCLASS_CLK, 0, clk_devp);
if (ret)
return ret;
ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clocks",
cell, 2);
if (ret)
return ret;
return cell[1];
#else
struct fdtdec_phandle_args args;
struct udevice *dev_clk;
struct clk_ops *ops;
debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
assert(*clk_devp);
assert(clk);
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
"clocks", "#clock-cells", 0, index,
&args);
......@@ -95,16 +82,117 @@ int clk_get_by_index(struct udevice *dev, int index, struct udevice **clk_devp)
return ret;
}
ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, clk_devp);
ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev_clk);
if (ret) {
debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
__func__, ret);
return ret;
}
return args.args_count > 0 ? args.args[0] : 0;
#endif
ops = clk_dev_ops(dev_clk);
if (ops->of_xlate)
ret = ops->of_xlate(clk, &args);
else
ret = clk_of_xlate_default(clk, &args);
if (ret) {
debug("of_xlate() failed: %d\n", ret);
return ret;
}
return clk_request(dev_clk, clk);
}
int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
{
int index;
debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
index = fdt_find_string(gd->fdt_blob, dev->of_offset, "clock-names",
name);
if (index < 0) {
debug("fdt_find_string() failed: %d\n", index);
return index;
}
return clk_get_by_index(dev, index, clk);
}
#endif
#endif
int clk_request(struct udevice *dev, struct clk *clk)
{
struct clk_ops *ops = clk_dev_ops(dev);
debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
clk->dev = dev;
if (!ops->request)
return 0;
return ops->request(clk);
}
int clk_free(struct clk *clk)
{
struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
if (!ops->free)
return 0;
return ops->free(clk);
}
ulong clk_get_rate(struct clk *clk)
{
struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
if (!ops->get_rate)
return -ENOSYS;
return ops->get_rate(clk);
}
ulong clk_set_rate(struct clk *clk, ulong rate)
{
struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
if (!ops->set_rate)
return -ENOSYS;
return ops->set_rate(clk, rate);
}
int clk_enable(struct clk *clk)
{
struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
if (!ops->enable)
return -ENOSYS;
return ops->enable(clk);
}
int clk_disable(struct clk *clk)
{
struct clk_ops *ops = clk_dev_ops(clk->dev);
debug("%s(clk=%p)\n", __func__, clk);
if (!ops->disable)
return -ENOSYS;
return ops->disable(clk);
}
UCLASS_DRIVER(clk) = {
.id = UCLASS_CLK,
......
......@@ -5,7 +5,7 @@
*/
#include <common.h>
#include <clk.h>
#include <clk-uclass.h>
#include <dm/device.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -16,19 +16,16 @@ struct clk_fixed_rate {
#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
static ulong clk_fixed_rate_get_rate(struct udevice *dev)
static ulong clk_fixed_rate_get_rate(struct clk *clk)
{
return to_clk_fixed_rate(dev)->fixed_rate;
}
if (clk->id != 0)
return -EINVAL;
static ulong clk_fixed_rate_get_periph_rate(struct udevice *dev, int periph)
{
return clk_fixed_rate_get_rate(dev);
return to_clk_fixed_rate(clk->dev)->fixed_rate;
}
const struct clk_ops clk_fixed_rate_ops = {