Commit 1489e2b3 authored by Ye Li's avatar Ye Li Committed by Jason Liu

MLK-14938-26 imx8qm_arm2: Add i.MX8QM ARM2 board support

Add board level codes and DTS for i.MX8QM LPDDR4 ARM2 board.

Copy the DTS from imx_4.9.y kernel on commit:
"f4b0affd5477301f732efc8ee21185b11495cfcf"
With modifications to support FlexSPI flash and PCA953x

- Enabled DM driver:
  FEC, LPUART, LPI2C, GPIO, SD/MMC, FSPI, PCA953X

- Enabled Non-DM driver:
  SATA, PCIE, iomux, fuse

- Disabled driver:
  mailbox, pinctrl (will try to use later)

- Board defconfigs:
  imx8qm_lpddr4_arm2_defconfig
Signed-off-by: 's avatarShenwei Wang <shenwei.wang@nxp.com>
Signed-off-by: 's avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: 's avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: 's avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: 's avatarFugang Duan <fugang.duan@nxp.com>
Signed-off-by: 's avatarRichard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: 's avatarHan Xu <han.xu@nxp.com>
Signed-off-by: 's avatarPeter Chen <peter.chen@nxp.com>
Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
parent 0e69d9e7
......@@ -25,4 +25,20 @@ config IMX8QXP
config SYS_SOC
default "imx8"
choice
prompt "MX8 board select"
optional
config TARGET_IMX8QM_LPDDR4_ARM2
bool "Support i.MX8QM lpddr4 validation board"
select IMX8QM
config TARGET_IMX8QM_DDR4_ARM2
bool "Support i.MX8QM ddr4 validation board"
select IMX8QM
endchoice
source "board/freescale/imx8qm_arm2/Kconfig"
endif
......@@ -386,6 +386,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb \
imx7ulp-10x10-arm2.dtb \
imx7ulp-14x14-arm2.dtb
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qm-lpddr4-arm2.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
keystone-k2e-evm.dtb \
......
This diff is collapsed.
if TARGET_IMX8QM_LPDDR4_ARM2 || TARGET_IMX8QM_DDR4_ARM2
config SYS_BOARD
default "imx8qm_arm2"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "imx8qm_arm2"
endif
#
# Copyright 2017 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx8qm_arm2.o
This diff is collapsed.
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-arm2"
CONFIG_TARGET_IMX8QM_LPDDR4_ARM2=y
CONFIG_CMD_IMPORTENV=n
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_OF_CONTROL=y
CONFIG_DM_I2C=y
# CONFIG_DM_I2C_COMPAT is not set
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_USB is not set
# CONFIG_USB is not set
CONFIG_CMD_GPIO=y
CONFIG_DM_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_BOOTDELAY=3
CONFIG_IMX_BOOTAUX=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MMC=y
CONFIG_DM_MMC=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_FSL_FSPI=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_SF=y
CONFIG_CMD_PING=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_DM_ETH=y
# CONFIG_EFI_LOADER is not set
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMX8QM_ARM2_H
#define __IMX8QM_ARM2_H
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
#define CONFIG_REMAKE_ELF
#define CONFIG_BOARD_EARLY_INIT_F
/* Flat Device Tree Definitions */
#define CONFIG_OF_BOARD_SETUP
#undef CONFIG_CMD_EXPORTENV
#undef CONFIG_CMD_IMPORTENV
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_CRC32
#undef CONFIG_BOOTM_NETBSD
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define USDHC3_BASE_ADDR 0x5B030000
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SCSI
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_CMD_SCSI
#define CONFIG_LIBATA
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_SATA_IMX
#define CONFIG_FSL_HSIO
#define CONFIG_PCIE_IMX8X
#define CONFIG_CMD_PCI
#define CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
/* FUSE command */
#define CONFIG_CMD_FUSE
/* GPIO configs */
#define CONFIG_MXC_GPIO
/* ENET Config */
#define CONFIG_MII
#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define FEC_QUIRK_ENET_MAC
#define CONFIG_PHY_GIGE /* Support for 1000BASE-X */
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */
#define CONFIG_FEC_ENET_DEV 0
#if (CONFIG_FEC_ENET_DEV == 0)
#define IMX_FEC_BASE 0x5B040000
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CONFIG_ETHPRIME "eth0"
#elif (CONFIG_FEC_ENET_DEV == 1)
#define IMX_FEC_BASE 0x5B050000
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_FEC_ENABLE_MAX7322
#define CONFIG_ETHPRIME "eth1"
#endif
/* ENET0 MDIO are shared */
#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000
/* MAX7322 */
#ifdef CONFIG_FEC_ENABLE_MAX7322
#define CONFIG_MAX7322_I2C_ADDR 0x68
#define CONFIG_MAX7322_I2C_BUS 2 /* I2C2 */
#endif
/* Boot M4 */
#define M4_BOOT_ENV \
"m4_0_image=m4_0.bin\0" \
"m4_1_image=m4_1.bin\0" \
"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
"loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
"m4boot_0=run loadm4image_0; bootaux ${loadaddr} 0\0" \
"m4boot_1=run loadm4image_1; bootaux ${loadaddr} 1\0" \
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
M4_BOOT_ENV \
"script=boot.scr\0" \
"image=Image\0" \
"mmcdev=1\0"\
"console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200\0" \
"fdtaddr=0x83000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fdt=try\0" \
"fdt_file=fsl-imx8qm-lpddr4-arm2.dtb\0" \
"initrd_addr=0x83800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} " \
"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"booti ${loadaddr} - ${fdtaddr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"else " \
"echo wait for boot; " \
"fi;\0" \
"netargs=setenv bootargs console=${console} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${loadaddr} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdtaddr} ${fdt_file}; then " \
"booti ${loadaddr} - ${fdtaddr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"else " \
"booti; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"else booti ${loadaddr} - ${fdtaddr}; " \
"fi; " \
"fi; " \
"else booti ${loadaddr} - ${fdtaddr}; fi"
/* Link Definitions */
#define CONFIG_LOADADDR 0x80080000
#define CONFIG_SYS_TEXT_BASE 0x80020000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_SP_ADDR 0x90000000
/* Default environment is in SD */
#define CONFIG_ENV_OFFSET (14 * SZ_64K)
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board, USDHC3 is for SD on base board
* On DDR4 board, USDHC1 is mux for NAND, USDHC2 is for SD, USDHC3 is for SD on base board
*/
#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 3
#else
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#endif
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (16*1024)) * 1024)
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
/* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4GB */
#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
#else
#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
#endif
/* Serial */
#define CONFIG_BAUDRATE 115200
/* Monitor Command Prompt */
#define CONFIG_SYS_LONGHELP
#define CONFIG_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_CMDLINE_EDITING
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
#ifndef CONFIG_DM_PCA953X
#define CONFIG_PCA953X
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#endif
#define CONFIG_IMX_SMMU
/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */
#ifdef CONFIG_FSL_FSPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define FSL_FSPI_FLASH_SIZE SZ_64M
#define FSL_FSPI_FLASH_NUM 1
#define FSPI0_BASE_ADDR 0x5d120000
#define FSPI0_AMBA_BASE 0
#define CONFIG_SYS_FSL_FSPI_AHB
#endif
#endif /* __IMX8QM_ARM2_H */
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