Commit 1a2621ba authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Nobuhiro Iwamatsu

sh: add support for sh7752evb board

The R0P7752C00000RZ board has SH7752, 512MB DDR3-SDRAM, SPI ROM,
Gigabit Ethernet, and eMMC.

This patch supports the following functions:
 - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC
Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: default avatarNobuhiro Iwamatsu <iwamatsu@nigauri.org>
parent 09572880
......@@ -1202,6 +1202,7 @@ Mark Jonas <mark.jonas@de.bosch.com>
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
MS7720SE SH7720
R0P77520000RZ SH7752
R0P77570030RL SH7757
R0P77850011RL SH7785
......
......@@ -48,6 +48,8 @@
# include <asm/cpu_sh7724.h>
#elif defined (CONFIG_CPU_SH7734)
# include <asm/cpu_sh7734.h>
#elif defined (CONFIG_CPU_SH7752)
# include <asm/cpu_sh7752.h>
#elif defined (CONFIG_CPU_SH7757)
# include <asm/cpu_sh7757.h>
#elif defined (CONFIG_CPU_SH7763)
......
/*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _ASM_CPU_SH7752_H_
#define _ASM_CPU_SH7752_H_
#define CCR 0xFF00001C
#define WTCNT 0xFFCC0000
#define CCR_CACHE_INIT 0x0000090b
#define CACHE_OC_NUM_WAYS 1
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
/* MMU */
struct mmu_regs {
unsigned int reserved[4];
unsigned int mmucr;
};
#define MMU_BASE ((struct mmu_regs *)0xff000000)
/* Watchdog */
#define WTCSR0 0xffcc0002
#define WRSTCSR_R 0xffcc0003
#define WRSTCSR_W 0xffcc0002
#define WTCSR_PREFIX 0xa500
#define WRSTCSR_PREFIX 0x6900
#define WRSTCSR_WOVF_PREFIX 0x9600
/* SCIF */
#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
/* TMU0 */
#define TMU_BASE 0xFE430000
/* ETHER, GETHER MAC address */
struct ether_mac_regs {
unsigned int reserved[114];
unsigned int mahr;
unsigned int reserved2;
unsigned int malr;
};
#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
/* GETHER */
struct gether_control_regs {
unsigned int gbecont;
};
#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
#define GBECONT_RMII1 0x00020000
#define GBECONT_RMII0 0x00010000
/* SerMux */
struct sermux_regs {
unsigned char smr0;
unsigned char smr1;
unsigned char smr2;
unsigned char smr3;
unsigned char smr4;
unsigned char smr5;
};
#define SERMUX_BASE ((struct sermux_regs *)0xfe470000)
/* USB0/1 */
struct usb_common_regs {
unsigned short reserved[129];
unsigned short suspmode;
};
#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
struct usb0_phy_regs {
unsigned short reset;
unsigned short reserved[4];
unsigned short portsel;
};
#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
struct usb1_port_regs {
unsigned int port1sel;
unsigned int reserved;
unsigned int usb1intsts;
};
#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
struct usb1_alignment_regs {
unsigned int ehcidatac; /* 0xfe4fe018 */
unsigned int reserved[63];
unsigned int ohcidatac;
};
#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
/* GPIO */
struct gpio_regs {
unsigned short pacr;
unsigned short pbcr;
unsigned short pccr;
unsigned short pdcr;
unsigned short pecr;
unsigned short pfcr;
unsigned short pgcr;
unsigned short phcr;
unsigned short picr;
unsigned short pjcr;
unsigned short pkcr;
unsigned short plcr;
unsigned short pmcr;
unsigned short pncr;
unsigned short pocr;
unsigned short reserved;
unsigned short pqcr;
unsigned short prcr;
unsigned short pscr;
unsigned short ptcr;
unsigned short pucr;
unsigned short pvcr;
unsigned short pwcr;
unsigned short pxcr;
unsigned short pycr;
unsigned short pzcr;
unsigned char padr;
unsigned char reserved_a;
unsigned char pbdr;
unsigned char reserved_b;
unsigned char pcdr;
unsigned char reserved_c;
unsigned char pddr;
unsigned char reserved_d;
unsigned char pedr;
unsigned char reserved_e;
unsigned char pfdr;
unsigned char reserved_f;
unsigned char pgdr;
unsigned char reserved_g;
unsigned char phdr;
unsigned char reserved_h;
unsigned char pidr;
unsigned char reserved_i;
unsigned char pjdr;
unsigned char reserved_j;
unsigned char pkdr;
unsigned char reserved_k;
unsigned char pldr;
unsigned char reserved_l;
unsigned char pmdr;
unsigned char reserved_m;
unsigned char pndr;
unsigned char reserved_n;
unsigned char podr;
unsigned char reserved_o;
unsigned char ppdr;
unsigned char reserved_p;
unsigned char pqdr;
unsigned char reserved_q;
unsigned char prdr;
unsigned char reserved_r;
unsigned char psdr;
unsigned char reserved_s;
unsigned char ptdr;
unsigned char reserved_t;
unsigned char pudr;
unsigned char reserved_u;
unsigned char pvdr;
unsigned char reserved_v;
unsigned char pwdr;
unsigned char reserved_w;
unsigned char pxdr;
unsigned char reserved_x;
unsigned char pydr;
unsigned char reserved_y;
unsigned char pzdr;
unsigned char reserved_z;
unsigned short ncer;
unsigned short ncmcr;
unsigned short nccsr;
unsigned char reserved2[2];
unsigned short psel0; /* +0x70 */
unsigned short psel1;
unsigned short psel2;
unsigned short psel3;
unsigned short psel4;
unsigned short psel5;
unsigned short psel6;
unsigned short reserved3[2];
unsigned short psel7;
};
#define GPIO_BASE ((struct gpio_regs *)0xffec0000)
#endif /* ifndef __ASSEMBLY__ */
#endif /* _ASM_CPU_SH7752_H_ */
#
# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := sh7752evb.o spi-boot.o
SOBJS := lowlevel_init.o
$(LIB): $(obj).depend $(COBJS) $(SOBJS)
$(call cmd_link_o_target, $(COBJS) $(SOBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
This diff is collapsed.
/*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmc.h>
#include <spi_flash.h>
int checkboard(void)
{
puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
return 0;
}
static void init_gpio(void)
{
struct gpio_regs *gpio = GPIO_BASE;
struct sermux_regs *sermux = SERMUX_BASE;
/* GPIO */
writew(0x0000, &gpio->pacr); /* GETHER */
writew(0x0001, &gpio->pbcr); /* INTC */
writew(0x0000, &gpio->pccr); /* PWMU, INTC */
writew(0xeaff, &gpio->pecr); /* GPIO */
writew(0x0000, &gpio->pfcr); /* WDT */
writew(0x0000, &gpio->phcr); /* SPI1 */
writew(0x0000, &gpio->picr); /* SDHI */
writew(0x0003, &gpio->pkcr); /* SerMux */
writew(0x0000, &gpio->plcr); /* SerMux */
writew(0x0000, &gpio->pmcr); /* RIIC */
writew(0x0000, &gpio->pncr); /* USB, SGPIO */
writew(0x0000, &gpio->pocr); /* SGPIO */
writew(0xd555, &gpio->pqcr); /* GPIO */
writew(0x0000, &gpio->prcr); /* RIIC */
writew(0x0000, &gpio->pscr); /* RIIC */
writeb(0x00, &gpio->pudr);
writew(0x5555, &gpio->pucr); /* Debug LED */
writew(0x0000, &gpio->pvcr); /* RSPI */
writew(0x0000, &gpio->pwcr); /* EVC */
writew(0x0000, &gpio->pxcr); /* LBSC */
writew(0x0000, &gpio->pycr); /* LBSC */
writew(0x0000, &gpio->pzcr); /* eMMC */
writew(0xfe00, &gpio->psel0);
writew(0xff00, &gpio->psel3);
writew(0x771f, &gpio->psel4);
writew(0x00ff, &gpio->psel6);
writew(0xfc00, &gpio->psel7);
writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
}
static void init_usb_phy(void)
{
struct usb_common_regs *common0 = USB0_COMMON_BASE;
struct usb_common_regs *common1 = USB1_COMMON_BASE;
struct usb0_phy_regs *phy = USB0_PHY_BASE;
struct usb1_port_regs *port = USB1_PORT_BASE;
struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
writew(0x0100, &phy->reset); /* set reset */
/* port0 = USB0, port1 = USB1 */
writew(0x0002, &phy->portsel);
writel(0x0001, &port->port1sel); /* port1 = Host */
writew(0x0111, &phy->reset); /* clear reset */
writew(0x4000, &common0->suspmode);
writew(0x4000, &common1->suspmode);
#if defined(__LITTLE_ENDIAN)
writel(0x00000000, &align->ehcidatac);
writel(0x00000000, &align->ohcidatac);
#endif
}
static void init_gether_mdio(void)
{
struct gpio_regs *gpio = GPIO_BASE;
writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
}
static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
{
struct ether_mac_regs *ether;
unsigned char mac[6];
unsigned long val;
eth_parse_enetaddr(mac_string, mac);
if (!channel)
ether = GETHER0_MAC_BASE;
else
ether = GETHER1_MAC_BASE;
val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
writel(val, &ether->mahr);
val = (mac[4] << 8) | mac[5];
writel(val, &ether->malr);
}
/*****************************************************************
* This PMB must be set on this timing. The lowlevel_init is run on
* Area 0(phys 0x00000000), so we have to map it.
*
* The new PMB table is following:
* ent virt phys v sz c wt
* 0 0xa0000000 0x40000000 1 128M 0 1
* 1 0xa8000000 0x48000000 1 128M 0 1
* 2 0xb0000000 0x50000000 1 128M 0 1
* 3 0xb8000000 0x58000000 1 128M 0 1
* 4 0x80000000 0x40000000 1 128M 1 1
* 5 0x88000000 0x48000000 1 128M 1 1
* 6 0x90000000 0x50000000 1 128M 1 1
* 7 0x98000000 0x58000000 1 128M 1 1
*/
static void set_pmb_on_board_init(void)
{
struct mmu_regs *mmu = MMU_BASE;
/* clear ITLB */
writel(0x00000004, &mmu->mmucr);
/* delete PMB for SPIBOOT */
writel(0, PMB_ADDR_BASE(0));
writel(0, PMB_DATA_BASE(0));
/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
/* ppn ub v s1 s0 c wt */
writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
}
int board_init(void)
{
init_gpio();
set_pmb_on_board_init();
init_usb_phy();
init_gether_mdio();
return 0;
}
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
return 0;
}
int board_mmc_init(bd_t *bis)
{
struct gpio_regs *gpio = GPIO_BASE;
writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
udelay(1);
writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
udelay(200);
return mmcif_mmc_init();
}
static int get_sh_eth_mac_raw(unsigned char *buf, int size)
{
struct spi_flash *spi;
int ret;
spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
if (spi == NULL) {
printf("%s: spi_flash probe failed.\n", __func__);
return 1;
}
ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
if (ret) {
printf("%s: spi_flash read failed.\n", __func__);
spi_flash_free(spi);
return 1;
}
spi_flash_free(spi);
return 0;
}
static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
{
memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
SH7752EVB_ETHERNET_MAC_SIZE);
mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
return 0;
}
static void init_ethernet_mac(void)
{
char mac_string[64];
char env_string[64];
int i;
unsigned char *buf;
buf = malloc(256);
if (!buf) {
printf("%s: malloc failed.\n", __func__);
return;
}
get_sh_eth_mac_raw(buf, 256);
/* Gigabit Ethernet */
for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
get_sh_eth_mac(i, mac_string, buf);
if (i == 0)
setenv("ethaddr", mac_string);
else {
sprintf(env_string, "eth%daddr", i);
setenv(env_string, mac_string);
}
set_mac_to_sh_giga_eth_register(i, mac_string);
}
free(buf);
}
int board_late_init(void)
{
init_ethernet_mac();
return 0;
}
int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i, ret;
char mac_string[256];
struct spi_flash *spi;
unsigned char *buf;
if (argc != 3) {
buf = malloc(256);
if (!buf) {
printf("%s: malloc failed.\n", __func__);
return 1;
}
get_sh_eth_mac_raw(buf, 256);
/* print current MAC address */
for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
get_sh_eth_mac(i, mac_string, buf);
printf("GETHERC ch%d = %s\n", i, mac_string);
}
free(buf);
return 0;
}
/* new setting */
memset(mac_string, 0xff, sizeof(mac_string));
sprintf(mac_string, "%s\t%s",
argv[1], argv[2]);
/* write MAC data to SPI rom */
spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
if (!spi) {
printf("%s: spi_flash probe failed.\n", __func__);
return 1;
}
ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
SH7752EVB_SPI_SECTOR_SIZE);
if (ret) {
printf("%s: spi_flash erase failed.\n", __func__);
return 1;
}
ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
sizeof(mac_string), mac_string);
if (ret) {
printf("%s: spi_flash write failed.\n", __func__);
spi_flash_free(spi);
return 1;
}
spi_flash_free(spi);
puts("The writing of the MAC address to SPI ROM was completed.\n");
return 0;
}
U_BOOT_CMD(
write_mac, 3, 1, do_write_mac,
"write MAC address for GETHERC",
"[GETHERC ch0] [GETHERC ch1]\n"
);
/*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License. See the file "COPYING.LIB" in the main
* directory of this archive for more details.
*/
#include <common.h>
#define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE
#define CONFIG_SPI_ADDR 0x00000000
#define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN
#define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE
#define SPIWDMADR 0xFE001018
#define SPIWDMCNTR 0xFE001020
#define SPIDMCOR 0xFE001028
#define SPIDMINTSR 0xFE001188
#define SPIDMINTMR 0xFE001190
#define SPIDMINTSR_DMEND 0x00000004
#define TBR 0xFE002000
#define RBR 0xFE002000
#define CR1 0xFE002008
#define CR2 0xFE002010
#define CR3 0xFE002018
#define CR4 0xFE002020
/* CR1 */
#define SPI_TBE 0x80
#define SPI_TBF 0x40
#define SPI_RBE 0x20
#define SPI_RBF 0x10
#define SPI_PFONRD 0x08
#define SPI_SSDB 0x04
#define SPI_SSD 0x02
#define SPI_SSA 0x01
/* CR2 */
#define SPI_RSTF 0x80
#define SPI_LOOPBK 0x40
#define SPI_CPOL 0x20
#define SPI_CPHA 0x10
#define SPI_L1M0 0x08
/* CR4 */
#define SPI_TBEI 0x80
#define SPI_TBFI 0x40
#define SPI_RBEI 0x20
#define SPI_RBFI 0x10
#define SPI_SpiS0 0x02
#define SPI_SSS 0x01
#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
#define spi_read(addr) (*(volatile unsigned long *)(addr))
/* M25P80 */
#define M25_READ 0x03
#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
static void __uses_spiboot2 spi_reset(void)
{
int timeout = 0x00100000;
/* Make sure the last transaction is finalized */
spi_write(0x00, CR3);
spi_write(0x02, CR1);
while (!(spi_read(CR4) & SPI_SpiS0)) {
if (timeout-- < 0)
break;
}
spi_write(0x00, CR1);
spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
spi_write(0, SPIDMCOR);
}
static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
unsigned long len)
{
spi_write(M25_READ, TBR);
spi_write((addr >> 16) & 0xFF, TBR);
spi_write((addr >> 8) & 0xFF, TBR);
spi_write(addr & 0xFF, TBR);
spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
spi_write((unsigned long)buf, SPIWDMADR);
spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
spi_write(1, SPIDMCOR);
spi_write(0xff, CR3);
spi_write(spi_read(CR1) | SPI_SSDB, CR1);
spi_write(spi_read(CR1) | SPI_SSA, CR1);
while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
;
/* Nagate SP0-SS0 */
spi_write(0, CR1);
}
void __uses_spiboot2 spiboot_main(void)
{
void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
spi_reset();
spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
CONFIG_SPI_LENGTH);
_start();
}
/*
* Copyright (C) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* Copyright (C) 2012
* Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of