Commit 1d63b8ff authored by Anatolij Gustschin's avatar Anatolij Gustschin Committed by Wolfgang Denk

mpc512x: optionally configure DIU, LPC and NFC deviders

If a board config file defines DIU, LPC and NFC deviders,
configure them in the SCFR1 register.
Signed-off-by: default avatarAnatolij Gustschin <agust@denx.de>
parent e5f53864
......@@ -172,6 +172,21 @@ void cpu_init_f (volatile immap_t * im)
ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
out_be32(&im->clk.scfr[0], ips_div);
#ifdef SCFR1_LPC_DIV
clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK,
SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT);
#endif
#ifdef SCFR1_NFC_DIV
clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK,
SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT);
#endif
#ifdef SCFR1_DIU_DIV
clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK,
SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT);
#endif
/*
* Enable Time Base/Decrementer
*
......
......@@ -238,6 +238,12 @@ typedef struct clk512x {
#define SCFR1_LPC_DIV_MASK 0x00003800
#define SCFR1_LPC_DIV_SHIFT 11
#define SCFR1_NFC_DIV_MASK 0x00000700
#define SCFR1_NFC_DIV_SHIFT 8
#define SCFR1_DIU_DIV_MASK 0x000000FF
#define SCFR1_DIU_DIV_SHIFT 0
/* SCFR2 System Clock Frequency Register 2 */
#define SCFR2_SYS_DIV 0xFC000000
#define SCFR2_SYS_DIV_SHIFT 26
......
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