Commit 1fa3a634 authored by Stephen Warren's avatar Stephen Warren Committed by Tom Warren

ARM: tegra: Tegra114 pinmux cleanup

This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.

The entries in tegra114_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

This introduces a few changes to pin/group/function naming and the set of
available functions for each pin. The new values now exactly match the
TRM; the chip documentation. I adjusted a few entries in
pinmux-config-dalmore.h due to this.
Signed-off-by: 's avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: 's avatarTom Warren <twarren@nvidia.com>
parent 803d01ed
......@@ -34,8 +34,8 @@ static void enable_cpu_power_rail(void)
debug("enable_cpu_power_rail entry\n");
/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
/*
* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
......
......@@ -29,20 +29,24 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_UART4:
switch (config) {
case FUNCMUX_UART4_GMI:
pinmux_set_func(PINGRP_GMI_A16, PMUX_FUNC_UARTD);
pinmux_set_func(PINGRP_GMI_A17, PMUX_FUNC_UARTD);
pinmux_set_func(PINGRP_GMI_A18, PMUX_FUNC_UARTD);
pinmux_set_func(PINGRP_GMI_A19, PMUX_FUNC_UARTD);
pinmux_set_io(PINGRP_GMI_A16, PMUX_PIN_OUTPUT);
pinmux_set_io(PINGRP_GMI_A17, PMUX_PIN_INPUT);
pinmux_set_io(PINGRP_GMI_A18, PMUX_PIN_INPUT);
pinmux_set_io(PINGRP_GMI_A19, PMUX_PIN_OUTPUT);
pinmux_tristate_disable(PINGRP_GMI_A16);
pinmux_tristate_disable(PINGRP_GMI_A17);
pinmux_tristate_disable(PINGRP_GMI_A18);
pinmux_tristate_disable(PINGRP_GMI_A19);
pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7,
PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0,
PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1,
PMUX_FUNC_UARTD);
pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7,
PMUX_FUNC_UARTD);
pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT);
pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT);
pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT);
pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT);
pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7);
pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0);
pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1);
pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7);
break;
}
break;
......
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment