Commit 20187fd1 authored by Hao Zhang's avatar Hao Zhang Committed by Tom Rini

ARM: keystone2: add MSMC cache coherency support for K2E SOC

This patch adds Keystone2 K2E SOC specific code to support
MSMC cache coherency. Also create header file for msmc to hold
its API.
Acked-by: 's avatarMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: 's avatarHao Zhang <hzhang@ti.com>
Signed-off-by: 's avatarIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
parent 4dca7f0a
......@@ -10,6 +10,7 @@
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
#include <asm/arch/msmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
......@@ -24,11 +25,12 @@ int arch_cpu_init(void)
chip_configuration_unlock();
icache_enable();
#ifdef CONFIG_SOC_K2HK
share_all_segments(8);
share_all_segments(9);
share_all_segments(10); /* QM PDSP */
share_all_segments(11); /* PCIE */
msmc_share_all_segments(8); /* TETRIS */
msmc_share_all_segments(9); /* NETCP */
msmc_share_all_segments(10); /* QM PDSP */
msmc_share_all_segments(11); /* PCIE 0 */
#ifdef CONFIG_SOC_K2E
msmc_share_all_segments(13); /* PCIE 1 */
#endif
/*
......
......@@ -8,7 +8,7 @@
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/msmc.h>
struct mpax {
u32 mpaxl;
......@@ -56,7 +56,7 @@ struct msms_regs {
};
void share_all_segments(int priv_id)
void msmc_share_all_segments(int priv_id)
{
struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
int j;
......
......@@ -180,7 +180,6 @@ static inline int cpu_revision(void)
return rev;
}
void share_all_segments(int priv_id);
int cpu_to_bus(u32 *ptr, u32 length);
void sdelay(unsigned long);
......
/*
* MSMC controller
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _MSMC_H_
#define _MSMC_H_
#include <asm/arch/hardware.h>
void msmc_share_all_segments(int priv_id);
#endif
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