Commit 21a257b9 authored by Zhichun Hua's avatar Zhichun Hua Committed by York Sun

armv8: Fix TCR macros for shareability attribute

For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.
Signed-off-by: default avatarZhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
parent 25195600
......@@ -93,8 +93,8 @@
#define TCR_ORGN_WBNWA (3 << 10)
#define TCR_ORGN_MASK (3 << 10)
#define TCR_SHARED_NON (0 << 12)
#define TCR_SHARED_OUTER (1 << 12)
#define TCR_SHARED_INNER (2 << 12)
#define TCR_SHARED_OUTER (2 << 12)
#define TCR_SHARED_INNER (3 << 12)
#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K (1 << 14)
#define TCR_TG0_16K (2 << 14)
......
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