Commit 222a3113 authored by pekon gupta's avatar pekon gupta Committed by Tom Rini

ARM: omap: clean redundant PISMO_xx macros used in OMAP3

PISMO_xx macros were used to define 'Platform Independent Storage MOdule'
related GPMC configurations. This patch
- Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided
  by current u-boot infrastructure.
- Removes unused redundant macros, which are no longer required after
  merging of common platform code in following commit
      commit a0a37183
      ARM: omap: merge GPMC initialization code for all platform

+-----------------+-----------------------------------------------------------+
| Macro           | Reason for removal                                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE                         |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE                      |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so     |
|                 | configuring GPMC chip-select for smallest allowable       |
|                 | segment (GPMC_SIZE_16M) is enough.                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of    |
|                 | 128MB (GPMC_SIZE_128M)                                    |
+-----------------+-----------------------------------------------------------+
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR      |  Unused Macros                                            |
| PISMO1_NAND     |                                                           |
| PISMO2_CS0      |                                                           |
| PISMO2_CS1      |                                                           |
| PISMO1_ONENAND  |                                                           |
| PISMO2_NAND_CS0 |                                                           |
| PISMO2_NAND_CS1 |                                                           |
| PISMO1_NOR_BASE |                                                           |
| PISMO1_NAND_BASE|                                                           |
| PISMO2_CS0_BASE |                                                           |
+-----------------+-----------------------------------------------------------+
Signed-off-by: 's avatarPekon Gupta <pekon@ti.com>
parent 77cd89e7
......@@ -115,8 +115,8 @@ void gpmc_init(void)
ONENAND_GPMC_CONFIG6,
0
};
u32 base = PISMO1_ONEN_BASE;
u32 size = PISMO1_ONEN_SIZE;
u32 size = GPMC_SIZE_128M;
u32 base = CONFIG_SYS_ONENAND_BASE;
#else
const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
u32 size = 0;
......
......@@ -59,13 +59,6 @@
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
#define PISMO1_NOR 1
#define PISMO1_NAND 2
#define PISMO2_CS0 3
#define PISMO2_CS1 4
#define PISMO1_ONENAND 5
#define DBG_MPDB 6
#define PISMO2_NAND_CS0 7
#define PISMO2_NAND_CS1 8
#endif /* endif _MEM_H_ */
......@@ -98,7 +98,6 @@ struct ctrl_id {
#define DEBUG_BASE 0x08000000 /* debug board */
#define NAND_BASE 0x30000000 /* NAND addr */
/* (actual size small port) */
#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
#define ONENAND_MAP 0x20000000 /* OneNand addr */
/* (actual size small port) */
/* SMS */
......
......@@ -427,20 +427,7 @@ enum {
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
#define PISMO1_NOR 1
#define PISMO1_NAND 2
#define PISMO2_CS0 3
#define PISMO2_CS1 4
#define PISMO1_ONENAND 5
#define DBG_MPDB 6
#define PISMO2_NAND_CS0 7
#define PISMO2_NAND_CS1 8
/* make it readable for the gpmc_init */
#define PISMO1_NOR_BASE FLASH_BASE
#define PISMO1_NAND_BASE NAND_BASE
#define PISMO2_CS0_BASE PISMO2_MAP1
#define PISMO1_ONEN_BASE ONENAND_MAP
#define DBG_MPDB_BASE DEBUG_BASE
#ifndef __ASSEMBLY__
......
......@@ -252,17 +252,12 @@
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#define CONFIG_SYS_FLASH_BASE NAND_BASE
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
......
......@@ -259,18 +259,13 @@
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#endif
/* Monitor at start of flash */
......
......@@ -258,9 +258,6 @@
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
......
......@@ -262,8 +262,6 @@
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/* NAND and environment organization */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_ENV_IS_IN_NAND 1
......
......@@ -251,10 +251,6 @@
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
......
......@@ -316,10 +316,6 @@
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
......
......@@ -220,8 +220,6 @@
#ifdef ONENAND_SUPPORT
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
......
......@@ -265,13 +265,8 @@
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#endif
/* Monitor at start of flash */
......
......@@ -95,9 +95,6 @@
/*
* PISMO support
*/
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
/* Monitor at start of flash - Reserve 2 sectors */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
......@@ -205,12 +202,12 @@
* NAND / OneNAND
*/
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#elif defined(CONFIG_CMD_ONENAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#endif
......
......@@ -146,8 +146,6 @@
*/
#ifdef CONFIG_BOOT_ONENAND
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
......@@ -158,7 +156,6 @@
#endif
#ifdef CONFIG_NAND
#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
......
......@@ -277,16 +277,12 @@
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#elif defined(CONFIG_CMD_ONENAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
#endif
/* Monitor at start of flash */
......
......@@ -173,12 +173,8 @@
0x01F00000) /* 31MB */
/* FLASH and environment organization */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#if defined(CONFIG_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#endif
/* Monitor at start of flash */
......
......@@ -220,15 +220,10 @@
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#endif
/* Monitor at start of flash */
......
......@@ -165,13 +165,8 @@
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#endif
/* Monitor at start of flash */
......
......@@ -181,10 +181,6 @@
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_IS_IN_NAND
......
......@@ -254,13 +254,8 @@
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#define CONFIG_SYS_FLASH_BASE NAND_BASE
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
......
......@@ -317,8 +317,6 @@
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/* NAND and environment organization */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
......
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