Commit 23e2da27 authored by Ye Li's avatar Ye Li Committed by Stefano Babic

imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculation

The checking with max frequency supported is not correct, because the temp
is calculated by max pre and post dividers. We can decrease any divider to
meet the max frequency limitation. Actually, the calculation below the codes
is doing this way to find best pre and post dividers.
Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
Reviewed-by: 's avatarStefano Babic <sbabic@denx.de>
parent 9655ebdd
......@@ -638,10 +638,6 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
}
temp = freq * max_pred * max_postd;
if (temp > max) {
puts("Please decrease freq, too large!\n");
return;
}
if (temp < min) {
/*
* Register: PLL_VIDEO
......
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