Commit 26ad30e9 authored by Simon Glass's avatar Simon Glass

rockchip: Add basic peripheral and clock definitions

Add header files for the peripherals and clocks supported on Rockchip
platforms. The particular implementation (and register set) for each is
SoC-specific, but it seems that the naming can be generic.
Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
parent 1f8f7730
/*
* (C) Copyright 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_ARCH_CLOCK_H
#define _ASM_ARCH_CLOCK_H
/* define pll mode */
#define RKCLK_PLL_MODE_SLOW 0
#define RKCLK_PLL_MODE_NORMAL 1
enum {
ROCKCHIP_SYSCON_NOC,
ROCKCHIP_SYSCON_GRF,
ROCKCHIP_SYSCON_SGRF,
ROCKCHIP_SYSCON_PMU,
};
/* Standard Rockchip clock numbers */
enum rk_clk_id {
CLK_OSC,
CLK_ARM,
CLK_DDR,
CLK_CODEC,
CLK_GENERAL,
CLK_NEW,
CLK_COUNT,
};
static inline int rk_pll_id(enum rk_clk_id clk_id)
{
return clk_id - 1;
}
/**
* rockchip_get_cru() - get a pointer to the clock/reset unit registers
*
* @return pointer to registers, or -ve error on error
*/
void *rockchip_get_cru(void);
#endif
/*
* Copyright 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set)
#define RK_SETBITS(set) RK_CLRSETBITS(0, set)
#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0)
#define TIMER7_BASE 0xff810020
#define rk_clrsetreg(addr, clr, set) writel((clr) << 16 | (set), addr)
#define rk_clrreg(addr, clr) writel((clr) << 16, addr)
#define rk_setreg(addr, set) writel(set, addr)
#endif
/*
* (C) Copyright 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_ARCH_PERIPH_H
#define _ASM_ARCH_PERIPH_H
/*
* The peripherals supported by the hardware. This is used to specify clocks
* and pinctrl settings. Some SoCs will not support all of these, but it
* provides a common reference for common drivers to use.
*/
enum periph_id {
PERIPH_ID_PWM0,
PERIPH_ID_PWM1,
PERIPH_ID_PWM2,
PERIPH_ID_PWM3,
PERIPH_ID_PWM4,
PERIPH_ID_I2C0,
PERIPH_ID_I2C1,
PERIPH_ID_I2C2,
PERIPH_ID_I2C3,
PERIPH_ID_I2C4,
PERIPH_ID_I2C5,
PERIPH_ID_SPI0,
PERIPH_ID_SPI1,
PERIPH_ID_SPI2,
PERIPH_ID_UART0,
PERIPH_ID_UART1,
PERIPH_ID_UART2,
PERIPH_ID_UART3,
PERIPH_ID_UART4,
PERIPH_ID_LCDC0,
PERIPH_ID_LCDC1,
PERIPH_ID_SDMMC0,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,
PERIPH_ID_HDMI,
PERIPH_ID_COUNT,
/* Some aliases */
PERIPH_ID_EMMC = PERIPH_ID_SDMMC0,
PERIPH_ID_SDCARD = PERIPH_ID_SDMMC1,
PERIPH_ID_UART_BT = PERIPH_ID_UART0,
PERIPH_ID_UART_BB = PERIPH_ID_UART1,
PERIPH_ID_UART_DBG = PERIPH_ID_UART2,
PERIPH_ID_UART_GPS = PERIPH_ID_UART3,
PERIPH_ID_UART_EXP = PERIPH_ID_UART4,
};
#endif
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment