Commit 2acfda12 authored by Minghuan Lian's avatar Minghuan Lian Committed by York Sun

armv8: ls2080a: Enable PCIe in defconfigs

The patch enables PCIe in ls2080a defconfigs and
removes unused PCIe related macro defines.
Signed-off-by: default avatarMinghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: default avatarHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: default avatarYork Sun <york.sun@nxp.com>
parent 831b4e0c
......@@ -107,14 +107,6 @@
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
/* LUT registers */
#define PCIE_LUT_BASE 0x80000
#define PCIE_LUT_LCTRL0 0x7F8
#define PCIE_LUT_DBG 0x7FC
#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
#define PCIE_LUT_ENABLE (1 << 31)
#define PCIE_LUT_ENTRY_COUNT 32
/* Device Configuration */
#define DCFG_BASE 0x01e00000
......
......@@ -21,7 +21,6 @@ CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
......@@ -33,3 +32,7 @@ CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
......@@ -21,7 +21,6 @@ CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
......@@ -31,3 +30,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
......@@ -30,7 +30,6 @@ CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
......@@ -40,3 +39,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
......@@ -22,7 +22,6 @@ CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
......@@ -32,3 +31,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
......@@ -21,7 +21,6 @@ CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
......@@ -33,3 +32,7 @@ CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
......@@ -21,7 +21,6 @@ CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
......@@ -31,3 +30,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
......@@ -27,7 +27,6 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
......@@ -35,3 +34,7 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
......@@ -171,29 +171,7 @@ unsigned long long get_qixis_addr(void);
#endif
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#ifdef CONFIG_LS2080A
#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
#endif
#define CONFIG_SYS_PCI_64BIT
#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
/* Command line configuration */
#define CONFIG_CMD_ENV
......
......@@ -347,7 +347,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_FSL_MEMAC
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
......
......@@ -291,7 +291,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_FSL_MEMAC
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
......
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