Commit 2c0a6f2d authored by Mike Frysinger's avatar Mike Frysinger

Blackfin: add support for BF51x parts

Signed-off-by: 's avatarMike Frysinger <vapier@gentoo.org>
parent 180e311f
......@@ -6,6 +6,18 @@
#ifndef __MACH_CDEF_BLACKFIN__
#define __MACH_CDEF_BLACKFIN__
#ifdef __ADSPBF512__
# include "mach-bf518/BF512_cdef.h"
#endif
#ifdef __ADSPBF514__
# include "mach-bf518/BF514_cdef.h"
#endif
#ifdef __ADSPBF516__
# include "mach-bf518/BF516_cdef.h"
#endif
#ifdef __ADSPBF518__
# include "mach-bf518/BF518_cdef.h"
#endif
#ifdef __ADSPBF522__
# include "mach-bf527/BF522_cdef.h"
#endif
......
......@@ -6,6 +6,26 @@
#ifndef __MACH_DEF_BLACKFIN__
#define __MACH_DEF_BLACKFIN__
#ifdef __ADSPBF512__
# include "mach-bf518/BF512_def.h"
# include "mach-bf518/anomaly.h"
# include "mach-bf518/def_local.h"
#endif
#ifdef __ADSPBF514__
# include "mach-bf518/BF514_def.h"
# include "mach-bf518/anomaly.h"
# include "mach-bf518/def_local.h"
#endif
#ifdef __ADSPBF516__
# include "mach-bf518/BF516_def.h"
# include "mach-bf518/anomaly.h"
# include "mach-bf518/def_local.h"
#endif
#ifdef __ADSPBF518__
# include "mach-bf518/BF518_def.h"
# include "mach-bf518/anomaly.h"
# include "mach-bf518/def_local.h"
#endif
#ifdef __ADSPBF522__
# include "mach-bf527/BF522_def.h"
# include "mach-bf527/anomaly.h"
......
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/* DO NOT EDIT THIS FILE
* Automatically generated by generate-cdef-headers.xsl
* DO NOT EDIT THIS FILE
*/
#ifndef __BFIN_CDEF_ADSP_BF514_proc__
#define __BFIN_CDEF_ADSP_BF514_proc__
#include "BF512_cdef.h"
#define bfin_read_RSI_PWR_CONTROL() bfin_read16(RSI_PWR_CONTROL)
#define bfin_write_RSI_PWR_CONTROL(val) bfin_write16(RSI_PWR_CONTROL, val)
#define bfin_read_RSI_CLK_CONTROL() bfin_read16(RSI_CLK_CONTROL)
#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
#define bfin_read_RSI_DATA_CONTROL() bfin_read16(RSI_DATA_CONTROL)
#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
#define bfin_read_RSI_STATUSCL() bfin_read16(RSI_STATUSCL)
#define bfin_write_RSI_STATUSCL(val) bfin_write16(RSI_STATUSCL, val)
#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
#define bfin_read_RSI_ESTAT() bfin_read16(RSI_ESTAT)
#define bfin_write_RSI_ESTAT(val) bfin_write16(RSI_ESTAT, val)
#define bfin_read_RSI_EMASK() bfin_read16(RSI_EMASK)
#define bfin_write_RSI_EMASK(val) bfin_write16(RSI_EMASK, val)
#define bfin_read_RSI_CONFIG() bfin_read16(RSI_CONFIG)
#define bfin_write_RSI_CONFIG(val) bfin_write16(RSI_CONFIG, val)
#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
#endif /* __BFIN_CDEF_ADSP_BF514_proc__ */
/* DO NOT EDIT THIS FILE
* Automatically generated by generate-def-headers.xsl
* DO NOT EDIT THIS FILE
*/
#ifndef __BFIN_DEF_ADSP_BF514_proc__
#define __BFIN_DEF_ADSP_BF514_proc__
#include "BF512_def.h"
#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
#endif /* __BFIN_DEF_ADSP_BF514_proc__ */
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/* DO NOT EDIT THIS FILE
* Automatically generated by generate-def-headers.xsl
* DO NOT EDIT THIS FILE
*/
#ifndef __BFIN_DEF_ADSP_BF516_proc__
#define __BFIN_DEF_ADSP_BF516_proc__
#include "BF514_def.h"
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
#endif /* __BFIN_DEF_ADSP_BF516_proc__ */
/* DO NOT EDIT THIS FILE
* Automatically generated by generate-cdef-headers.xsl
* DO NOT EDIT THIS FILE
*/
#ifndef __BFIN_CDEF_ADSP_BF518_proc__
#define __BFIN_CDEF_ADSP_BF518_proc__
#include "BF516_cdef.h"
#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL)
#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val)
#define bfin_read_EMAC_PTP_IE() bfin_read16(EMAC_PTP_IE)
#define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val)
#define bfin_read_EMAC_PTP_ISTAT() bfin_read16(EMAC_PTP_ISTAT)
#define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val)
#define bfin_read_EMAC_PTP_FOFF() bfin_read32(EMAC_PTP_FOFF)
#define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val)
#define bfin_read_EMAC_PTP_FV1() bfin_read32(EMAC_PTP_FV1)
#define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val)
#define bfin_read_EMAC_PTP_FV2() bfin_read32(EMAC_PTP_FV2)
#define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val)
#define bfin_read_EMAC_PTP_FV3() bfin_read32(EMAC_PTP_FV3)
#define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val)
#define bfin_read_EMAC_PTP_ADDEND() bfin_read32(EMAC_PTP_ADDEND)
#define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val)
#define bfin_read_EMAC_PTP_ACCR() bfin_read32(EMAC_PTP_ACCR)
#define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val)
#define bfin_read_EMAC_PTP_OFFSET() bfin_read32(EMAC_PTP_OFFSET)
#define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val)
#define bfin_read_EMAC_PTP_TIMELO() bfin_read32(EMAC_PTP_TIMELO)
#define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val)
#define bfin_read_EMAC_PTP_TIMEHI() bfin_read32(EMAC_PTP_TIMEHI)
#define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val)
#define bfin_read_EMAC_PTP_RXSNAPLO() bfin_read32(EMAC_PTP_RXSNAPLO)
#define bfin_write_EMAC_PTP_RXSNAPLO(val) bfin_write32(EMAC_PTP_RXSNAPLO, val)
#define bfin_read_EMAC_PTP_RXSNAPHI() bfin_read32(EMAC_PTP_RXSNAPHI)
#define bfin_write_EMAC_PTP_RXSNAPHI(val) bfin_write32(EMAC_PTP_RXSNAPHI, val)
#define bfin_read_EMAC_PTP_TXSNAPLO() bfin_read32(EMAC_PTP_TXSNAPLO)
#define bfin_write_EMAC_PTP_TXSNAPLO(val) bfin_write32(EMAC_PTP_TXSNAPLO, val)
#define bfin_read_EMAC_PTP_TXSNAPHI() bfin_read32(EMAC_PTP_TXSNAPHI)
#define bfin_write_EMAC_PTP_TXSNAPHI(val) bfin_write32(EMAC_PTP_TXSNAPHI, val)
#define bfin_read_EMAC_PTP_ALARMLO() bfin_read32(EMAC_PTP_ALARMLO)
#define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val)
#define bfin_read_EMAC_PTP_ALARMHI() bfin_read32(EMAC_PTP_ALARMHI)
#define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val)
#define bfin_read_EMAC_PTP_ID_OFF() bfin_read16(EMAC_PTP_ID_OFF)
#define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val)
#define bfin_read_EMAC_PTP_ID_SNAP() bfin_read32(EMAC_PTP_ID_SNAP)
#define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val)
#define bfin_read_EMAC_PTP_PPS_STARTLO() bfin_read32(EMAC_PTP_PPS_STARTLO)
#define bfin_write_EMAC_PTP_PPS_STARTLO(val) bfin_write32(EMAC_PTP_PPS_STARTLO, val)
#define bfin_read_EMAC_PTP_PPS_STARTHI() bfin_read32(EMAC_PTP_PPS_STARTHI)
#define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val)
#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD)
#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val)
#endif /* __BFIN_CDEF_ADSP_BF518_proc__ */
/* DO NOT EDIT THIS FILE
* Automatically generated by generate-def-headers.xsl
* DO NOT EDIT THIS FILE
*/
#ifndef __BFIN_DEF_ADSP_BF518_proc__
#define __BFIN_DEF_ADSP_BF518_proc__
#include "BF516_def.h"
#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */
#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */
#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */
#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */
#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */
#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */
#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */
#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */
#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */
#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */
#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */
#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */
#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */
#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */
#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */
#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */
#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */
#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */
#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */
#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */
#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
#endif /* __BFIN_DEF_ADSP_BF518_proc__ */
/*
* DO NOT EDIT THIS FILE
* This file is under version control at
* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
* - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
*/
/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
#if __SILICON_REVISION__ < 0
# error will not work on BF518 silicon version
#endif
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
#define ANOMALY_05000254 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
#define ANOMALY_05000405 (1)
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
#define ANOMALY_05000408 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
#define ANOMALY_05000421 (1)
/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
#define ANOMALY_05000422 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* Software System Reset Corrupts PLL_LOCKCNT Register */
#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
#define ANOMALY_05000431 (1)
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
#define ANOMALY_05000434 (1)
/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
/* Preboot Cannot be Used to Alter the PLL_DIV Register */
#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* Incorrect L1 Instruction Bank B Memory Map Location */
#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
/* PWM_TRIPB Signal Not Available on PG10 */
#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
/* PLL Latches Incorrect Settings During Reset */
#define ANOMALY_05000469 (1)
/* Incorrect Default MSEL Value in PLL_CTL */
#define ANOMALY_05000472 (1)
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000257 (0)
#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0)
#define ANOMALY_05000281 (0)
#define ANOMALY_05000283 (0)
#define ANOMALY_05000285 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0)
#define ANOMALY_05000315 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (0)
#define ANOMALY_05000357 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000371 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
#define ANOMALY_05000485 (0)
#endif
#include "gpio.h"
#include "portmux.h"
#include "ports.h"
#define CONFIG_BF51x 1 /* Linux glue */
/*
* Copyright (C) 2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_GPIO_H_
#define _MACH_GPIO_H_
#define MAX_BLACKFIN_GPIOS 41
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PG0 16
#define GPIO_PG1 17
#define GPIO_PG2 18
#define GPIO_PG3 19
#define GPIO_PG4 20
#define GPIO_PG5 21
#define GPIO_PG6 22
#define GPIO_PG7 23
#define GPIO_PG8 24
#define GPIO_PG9 25
#define GPIO_PG10 26
#define GPIO_PG11 27
#define GPIO_PG12 28
#define GPIO_PG13 29
#define GPIO_PG14 30
#define GPIO_PG15 31
#define GPIO_PH0 32
#define GPIO_PH1 33
#define GPIO_PH2 34
#define GPIO_PH3 35
#define GPIO_PH4 36
#define GPIO_PH5 37
#define GPIO_PH6 38
#define GPIO_PH7 39
#define GPIO_PH8 40
#define PORT_F GPIO_PF0
#define PORT_G GPIO_PG0
#define PORT_H GPIO_PH0
#endif /* _MACH_GPIO_H_ */
/*
* Copyright 2008-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
/* EMAC MII/RMII Port Mux */
#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
#define P_MII0 {\
P_MII0_ETxD0, \
P_MII0_ETxD1, \
P_MII0_ETxD2, \
P_MII0_ETxD3, \
P_MII0_ETxEN, \
P_MII0_TxCLK, \
P_MII0_PHYINT, \
P_MII0_COL, \
P_MII0_ERxD0, \
P_MII0_ERxD1, \
P_MII0_ERxD2, \
P_MII0_ERxD3, \
P_MII0_ERxDV, \
P_MII0_ERxCLK, \
P_MII0_ERxER, \
P_MII0_CRS, \
P_MII0_MDC, \
P_MII0_MDIO, 0}
#define P_RMII0 {\
P_MII0_ETxD0, \
P_MII0_ETxD1, \
P_MII0_ETxEN, \
P_MII0_ERxD0, \
P_MII0_ERxD1, \
P_MII0_ERxER, \
P_MII0_TxCLK, \
P_MII0_PHYINT, \
P_MII0_CRS, \
P_MII0_MDC, \
P_MII0_MDIO, 0}
/* PPI Port Mux */
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
/* SPI Port Mux */
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
/* SPORT Port Mux */
#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
/* UART Port Mux */
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
/* Timer */
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
/* DMA */
#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
/* TWI */
#define P_TWI0_SCL (P_DONTCARE)
#define P_TWI0_SDA (P_DONTCARE)
/* PWM */
#define P_PWM0_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
#define P_PWM0_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))