Commit 2fccd2d9 authored by Simon Glass's avatar Simon Glass

tegra: Convert tegra GPIO driver to use driver model

This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.

The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this all the banks are created as separate GPIO devices.

The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7,
..., Z0..Z7, AA0..AA7, etc.

Since driver model is not yet available before relocation, or in SPL, a
special function is provided for seaboard's SPL code.
Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
parent a4741111
......@@ -6,6 +6,8 @@
#ifndef _TEGRA_GPIO_H_
#define _TEGRA_GPIO_H_
#define TEGRA_GPIOS_PER_PORT 8
#define TEGRA_PORTS_PER_BANK 4
#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
#define GPIO_NAME_SIZE 20 /* gpio_request max label len */
......@@ -25,9 +27,14 @@ struct tegra_gpio_config {
u32 init:2;
};
/*
* Tegra-specific GPIO API
/**
* tegra_spl_gpio_direction_output() - set the output value of a GPIO
*
* This function is only used from SPL on seaboard, which needs to enable a
* GPIO to get the UART running. It could be done in U-Boot rather than SPL,
* but for now, this gets it working
*/
int tegra_spl_gpio_direction_output(int gpio, int value);
/**
* Configure a list of GPIOs
......@@ -37,8 +44,4 @@ struct tegra_gpio_config {
*/
void gpio_config_table(const struct tegra_gpio_config *config, int len);
void gpio_info(void);
#define gpio_status() gpio_info()
#endif /* TEGRA_GPIO_H_ */
......@@ -22,7 +22,7 @@ void gpio_early_init_uart(void)
#ifndef CONFIG_SPL_BUILD
gpio_request(GPIO_PI3, NULL);
#endif
gpio_direction_output(GPIO_PI3, 0);
tegra_spl_gpio_direction_output(GPIO_PI3, 0);
}
#endif
......
This diff is collapsed.
......@@ -20,6 +20,7 @@
#define CONFIG_DM
#define CONFIG_CMD_DM
#define CONFIG_DM_GPIO
#define CONFIG_SYS_TIMER_RATE 1000000
#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
......
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