Commit 345b77ba authored by Stefan Roese's avatar Stefan Roese Committed by Tom Rini

ppc4xx: Remove 4xx NAND booting support

As ppc4xx currently only supports the deprecated nand_spl infrastructure
and nobody seems to have time / resources to port this over to the newer
SPL infrastructure, lets remove NAND booting completely.

This should not affect the "normal", non NAND-booting ppc4xx platforms
that are currently supported.
Signed-off-by: default avatarStefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tirumala Marri <tmarri@apm.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Tested-by: default avatarMatthias Fuchs <matthias.fuchs@esd.eu>
parent dc116bd6
......@@ -49,7 +49,6 @@
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0)
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void update_rdcc(void)
{
u32 val;
......@@ -72,7 +71,6 @@ static void update_rdcc(void)
}
}
}
#endif
#if defined(CONFIG_440)
/*
......@@ -101,7 +99,6 @@ void dcbz_area(u32 start_address, u32 num_bytes);
#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
#if !defined(CONFIG_NAND_SPL)
/*-----------------------------------------------------------------------------+
* sdram_memsize
*-----------------------------------------------------------------------------*/
......@@ -217,7 +214,6 @@ void board_add_ram_info(int use_default)
val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
printf(", CL%d)", val);
}
#endif /* !CONFIG_NAND_SPL */
#if defined(CONFIG_SPD_EEPROM)
......@@ -2843,16 +2839,6 @@ static void test(void)
*---------------------------------------------------------------------------*/
phys_size_t initdram(int board_type)
{
/*
* Only run this SDRAM init code once. For NAND booting
* targets like Kilauea, we call initdram() early from the
* 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
* Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
* which calls initdram() again. This time the controller
* mustn't be reconfigured again since we're already running
* from SDRAM.
*/
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
unsigned long val;
#if defined(CONFIG_440)
......@@ -2969,12 +2955,10 @@ phys_size_t initdram(int board_type)
#endif
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*------------------------------------------------------------------
| DQS calibration.
+-----------------------------------------------------------------*/
DQS_autocalibration();
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
/*
......@@ -3009,13 +2993,10 @@ phys_size_t initdram(int board_type)
set_mcsr(get_mcsr());
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
return (CONFIG_SYS_MBYTES_SDRAM << 20);
}
#endif /* CONFIG_SPD_EEPROM */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#if defined(CONFIG_440)
u32 mfdcr_any(u32 dcr)
{
......@@ -3062,7 +3043,6 @@ void mtdcr_any(u32 dcr, u32 val)
}
}
#endif /* defined(CONFIG_440) */
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
inline void ppc4xx_ibm_ddr2_register_dump(void)
{
......
......@@ -27,12 +27,6 @@
#include "ecc.h"
/*
* Only compile the DDR auto-calibration code for NOR boot and
* not for NAND boot (NAND SPL and NAND U-Boot - NUB)
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define MAXBXCF 4
#define SDRAM_RXBAS_SHIFT_1M 20
......@@ -1231,9 +1225,3 @@ u32 DQS_autocalibration(void)
return 0;
}
#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
u32 DQS_autocalibration(void)
{
return 0;
}
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
......@@ -14,11 +14,7 @@ obj-y += kgdb.o
obj-y += 40x_spd_sdram.o
ifndef CONFIG_NAND_SPL
ifndef CONFIG_NAND_U_BOOT
obj-y += 44x_spd_ddr.o
endif
endif
obj-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o
obj-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o
obj-y += 4xx_pci.o
......
......@@ -182,16 +182,13 @@
.extern ext_bus_cntlr_init
#ifdef CONFIG_NAND_U_BOOT
.extern reconfig_tlb0
#endif
/*
* Set up GOT: Global Offset Table
*
* Use r12 to access the GOT
*/
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
#if !defined(CONFIG_SPL_BUILD)
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
......@@ -205,22 +202,7 @@
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
#endif /* CONFIG_NAND_SPL */
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
!defined(CONFIG_SPL_BUILD)
/*
* NAND U-Boot image is started from offset 0
*/
.text
#if defined(CONFIG_440)
bl reconfig_tlb0
#endif
GET_GOT
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
#endif
#endif /* CONFIG_SPL_BUILD */
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
/*
......@@ -255,9 +237,7 @@
*/
#if defined(CONFIG_440)
#if !defined(CONFIG_NAND_SPL)
.section .bootpg,"ax"
#endif
.globl _start_440
/**************************************************************************/
......@@ -511,7 +491,7 @@ tlbnx2: addi r4,r4,1 /* Next TLB */
* r3 - 1st arg to board_init(): IMMP pointer
* r4 - 2nd arg to board_init(): boot flag
*/
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
#if !defined(CONFIG_SPL_BUILD)
.text
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
......@@ -777,9 +757,6 @@ _start:
stwu r1,-8(r1) /* Save back chain and move SP */
stw r0,+12(r1) /* Save return addr (underflow vect) */
#ifdef CONFIG_NAND_SPL
bl nand_boot_common /* will not return */
#else
#ifndef CONFIG_SPL_BUILD
GET_GOT
#endif
......@@ -787,7 +764,6 @@ _start:
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
#endif
#endif /* CONFIG_440 */
......@@ -1050,9 +1026,6 @@ _start:
stw r0, +12(r1) /* Save return addr (underflow vect) */
#endif /* CONFIG_SYS_INIT_DCACHE_CS */
#ifdef CONFIG_NAND_SPL
bl nand_boot_common /* will not return */
#else
GET_GOT /* initialize GOT access */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
......@@ -1060,13 +1033,11 @@ _start:
bl board_init_f /* run first part of init code (from Flash) */
/* NOTREACHED - board_init_f() does not return */
#endif /* CONFIG_NAND_SPL */
#endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
/*----------------------------------------------------------------------- */
#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
#if !defined(CONFIG_SPL_BUILD)
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
......@@ -1632,7 +1603,7 @@ __440_msr_continue:
blr
function_epilog(dcbz_area)
#endif /* CONFIG_440 */
#endif /* CONFIG_NAND_SPL */
#endif /* CONFIG_SPL_BUILD */
/*------------------------------------------------------------------------------- */
/* Function: in8 */
......@@ -1981,75 +1952,3 @@ pll_wait:
blr
function_epilog(mftlb1)
#endif /* CONFIG_440 */
#if defined(CONFIG_NAND_SPL)
/*
* void nand_boot_relocate(dst, src, bytes)
*
* r3 = Destination address to copy code to (in SDRAM)
* r4 = Source address to copy code from
* r5 = size to copy in bytes
*/
nand_boot_relocate:
mr r6,r3
mr r7,r4
mflr r8
/*
* Copy SPL from icache into SDRAM
*/
subi r3,r3,4
subi r4,r4,4
srwi r5,r5,2
mtctr r5
..spl_loop:
lwzu r0,4(r4)
stwu r0,4(r3)
bdnz ..spl_loop
/*
* Calculate "corrected" link register, so that we "continue"
* in execution in destination range
*/
sub r3,r7,r6 /* r3 = src - dst */
sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
mtlr r8
blr
nand_boot_common:
/*
* First initialize SDRAM. It has to be available *before* calling
* nand_boot().
*/
lis r3,CONFIG_SYS_SDRAM_BASE@h
ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
bl initdram
/*
* Now copy the 4k SPL code into SDRAM and continue execution
* from there.
*/
lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
bl nand_boot_relocate
/*
* We're running from SDRAM now!!!
*
* It is necessary for 4xx systems to relocate from running at
* the original location (0xfffffxxx) to somewhere else (SDRAM
* preferably). This is because CS0 needs to be reconfigured for
* NAND access. And we can't reconfigure this CS when currently
* "running" from it.
*/
/*
* Finally call nand_boot() to load main NAND U-Boot image from
* NAND and jump to it.
*/
bl nand_boot /* will not return */
#endif /* CONFIG_NAND_SPL */
......@@ -17,7 +17,6 @@
extern void board_pll_init_f(void);
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void cram_bcr_write(u32 wr_val)
{
wr_val <<= 2;
......@@ -41,20 +40,9 @@ static void cram_bcr_write(u32 wr_val)
return;
}
#endif
phys_size_t initdram(int board_type)
{
#if defined(CONFIG_NAND_SPL)
u32 reg;
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
#endif
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
int i;
u32 val;
......@@ -88,7 +76,6 @@ phys_size_t initdram(int board_type)
/* Wait a short while, since for NAND booting this is too fast */
for (i=0; i<200000; i++)
;
#endif
return (CONFIG_SYS_MBYTES_RAM << 20);
}
......@@ -135,45 +135,3 @@ void board_pll_init_f(void)
mtcpr(CPR0_CLKUP, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */
#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
/*
* Get timebase clock frequency
*/
unsigned long get_tbclk(void)
{
unsigned long cpr_plld;
unsigned long cpr_primad;
unsigned long primad_cpudv;
unsigned long pllFbkDiv;
unsigned long freqProcessor;
/*
* Read PLL Mode registers
*/
mfcpr(CPR0_PLLD, cpr_plld);
/*
* Read CPR_PRIMAD register
*/
mfcpr(CPR0_PRIMAD, cpr_primad);
/*
* Determine CPU clock frequency
*/
primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
if (primad_cpudv == 0)
primad_cpudv = 16;
/*
* Determine FBK_DIV.
*/
pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
if (pllFbkDiv == 0)
pllFbkDiv = 256;
freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
return (freqProcessor);
}
#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
......@@ -16,7 +16,6 @@ void ext_bus_cntlr_init(void);
void configure_ppc440ep_pins(void);
int is_nand_selected(void);
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
/*************************************************************************
*
* Bamboo has one bank onboard sdram (plus DIMM)
......@@ -178,7 +177,6 @@ const unsigned char cfg_simulate_spd_eeprom[128] = {
0,
0
};
#endif
#if 0
{ /* GPIO Alternate1 Alternate2 Alternate3 */
......@@ -440,15 +438,11 @@ int checkboard(void)
phys_size_t initdram (int board_type)
{
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
long dram_size;
dram_size = spd_sdram();
return dram_size;
#else
return CONFIG_SYS_MBYTES_SDRAM << 20;
#endif
}
/*----------------------------------------------------------------------------+
......@@ -1794,23 +1788,12 @@ void configure_ppc440ep_pins(void)
if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
{
update_ndfc_ios(gpio_tab);
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_CHIPSELGAT_EN1 |
SDR0_CUST0_CHIPSELGAT_EN2);
#else
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_CHIPSELGAT_EN0 |
SDR0_CUST0_CHIPSELGAT_EN2);
#endif
ndfc_selection_in_fpga();
}
else
......
......@@ -32,12 +32,7 @@ tlbtab:
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
#ifndef CONFIG_NAND_SPL
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
#else
tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
#endif
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
......@@ -58,31 +53,3 @@ tlbtab:
tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*
* For NAND booting the first TLB has to be reconfigured to full size
* and with caching disabled after running from RAM!
*/
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
#define TLB02 TLB2(AC_RWX | SA_IG)
.globl reconfig_tlb0
reconfig_tlb0:
sync
isync
addi r4,r0,0x0000 /* TLB entry #0 */
lis r5,TLB00@h
ori r5,r5,TLB00@l
tlbwe r5,r4,0x0000 /* Save it out */
lis r5,TLB01@h
ori r5,r5,TLB01@l
tlbwe r5,r4,0x0001 /* Save it out */
lis r5,TLB02@h
ori r5,r5,TLB02@l
tlbwe r5,r4,0x0002 /* Save it out */
sync
isync
blr
#endif
......@@ -379,11 +379,7 @@ int board_early_init_r (void)
*/
/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#else
mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#endif
/* Remove TLB entry of boot EBC mapping */
remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
......
......@@ -31,13 +31,7 @@ tlbtab:
* use the speed up boot process. It is patched after relocation to
* enable SA_I
*/
#ifndef CONFIG_NAND_SPL
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
#else
tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G)
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG)
#endif
/*
* TLB entries for SDRAM are not needed on this platform.
......@@ -95,31 +89,3 @@ tlbtab:
#endif
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*
* For NAND booting the first TLB has to be reconfigured to full size
* and with caching disabled after running from RAM!
*/
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
#define TLB02 TLB2(AC_RWX | SA_IG)
.globl reconfig_tlb0
reconfig_tlb0:
sync
isync
addi r4,r0,0x0000 /* TLB entry #0 */
lis r5,TLB00@h
ori r5,r5,TLB00@l
tlbwe r5,r4,0x0000 /* Save it out */
lis r5,TLB01@h
ori r5,r5,TLB01@l
tlbwe r5,r4,0x0001 /* Save it out */
lis r5,TLB02@h
ori r5,r5,TLB02@l
tlbwe r5,r4,0x0002 /* Save it out */
sync
isync
blr
#endif
......@@ -48,11 +48,7 @@ tlbtab:
/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
#ifndef CONFIG_NAND_SPL
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
#else
tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
#endif
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
......@@ -81,31 +77,3 @@ tlbtab:
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*
* For NAND booting the first TLB has to be reconfigured to full size
* and with caching disabled after running from RAM!
*/
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
#define TLB02 TLB2(AC_RWX | SA_IG)
.globl reconfig_tlb0
reconfig_tlb0:
sync
isync
addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */
lis r5,TLB00@h
ori r5,r5,TLB00@l
tlbwe r5,r4,0x0000 /* Save it out */
lis r5,TLB01@h
ori r5,r5,TLB01@l
tlbwe r5,r4,0x0001 /* Save it out */
lis r5,TLB02@h
ori r5,r5,TLB02@l
tlbwe r5,r4,0x0002 /* Save it out */
sync
isync
blr
#endif
......@@ -26,14 +26,6 @@
extern int denali_wait_for_dlllock(void);
extern void denali_core_search_data_eye(void);
#if defined(CONFIG_NAND_SPL)
/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
* for the 4k NAND boot image so define bus_frequency to 133MHz here
* which is save for the refresh counter setup.
*/
#define get_bus_freq(val) 133333333
#endif
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
......@@ -41,8 +33,7 @@ extern void denali_core_search_data_eye(void);
************************************************************************/
phys_size_t initdram (int board_type)
{
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
defined(CONFIG_NAND_SPL)
#if !defined(CONFIG_SYS_RAMBOOT)
ulong speed = get_bus_freq(0);
mtsdram(DDR0_02, 0x00000000);
......@@ -81,7 +72,7 @@ phys_size_t initdram (int board_type)
mtsdram(DDR0_02, 0x00000001);
denali_wait_for_dlllock();
#endif /* #ifndef CONFIG_NAND_U_BOOT */
#endif /* #ifndef CONFIG_SYS_RAMBOOT */
#ifdef CONFIG_DDR_DATA_EYE
/* -----------------------------------------------------------+
......
......@@ -142,8 +142,7 @@ int misc_init_r(void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
......@@ -151,8 +150,7 @@ int misc_init_r(void)
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
......@@ -360,7 +358,7 @@ void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
}
#endif
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_SYS_RAMBOOT)
/*
* On NAND-booting sequoia, we need to patch the chips select numbers
* in the dtb (CS0 - NAND, CS3 - NOR)
......@@ -411,4 +409,4 @@ void ft_board_setup(void *blob, bd_t *bd)
return;
}
}
#endif /* CONFIG_NAND_U_BOOT */
#endif /* CONFIG_SYS_RAMBOOT */
......@@ -27,11 +27,7 @@ tlbtab:
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
#ifndef CONFIG_NAND_SPL
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
#else
tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
#endif
/* TLB entries for DDR2 SDRAM are generated dynamically */
......@@ -71,31 +67,3 @@ tlbtab:
/* TODO: what about high IO space */
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*
* For NAND booting the first TLB has to be reconfigured to full size
* and with caching disabled after running from RAM!
*/
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
#define TLB02 TLB2(AC_RWX | SA_IG)
.globl reconfig_tlb0
reconfig_tlb0:
sync
isync
addi r4,r0,0x0000 /* TLB entry #0 */
lis r5,TLB00@h
ori r5,r5,TLB00@l
tlbwe r5,r4,0x0000 /* Save it out */
lis r5,TLB01@h
ori r5,r5,TLB01@l
tlbwe r5,r4,0x0001 /* Save it out */
lis r5,TLB02@h
ori r5,r5,TLB02@l
tlbwe r5,r4,0x0002 /* Save it out */
sync
isync
blr
#endif
......@@ -229,19 +229,11 @@ int misc_init_r(void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(EBC0_CFGADDR, PB2CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
#endif
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(EBC0_CFGADDR, PB2CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
#endif
mtdcr(EBC0_CFGDATA, pbcr);
/*
......
......@@ -1121,22 +1121,14 @@ Active powerpc ppc4xx - amcc -
Active powerpc ppc4xx - amcc - taihu - John Otken <jotken@softadvances.com>
Active powerpc ppc4xx - amcc - taishan - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc - yucca - -
Active powerpc ppc4xx - amcc acadia acadia_nand acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc bamboo bamboo_nand bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands canyonlands_nand canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands glacier_nand canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea haleakala_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea kilauea_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia rainier_nand sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia sequoia_nand sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese <sr@denx.de>
......
......@@ -104,7 +104,6 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
*p++ = in_be32((u32 *)(base + NDFC_DATA));
}
#ifndef CONFIG_NAND_SPL
/*
* Don't use these speedup functions in NAND boot image, since the image
* has to fit into 4kByte.
......@@ -148,8 +147,6 @@ static uint8_t ndfc_read_byte(struct mtd_info *mtd)
}
#endif /* #ifndef CONFIG_NAND_SPL */
void board_nand_select_device(struct nand_chip *nand, int chip)