Commit 374e78ef authored by Simon Glass's avatar Simon Glass Committed by Bin Meng

x86: Add support for the samus chromebook

This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.

Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard

Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).

The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.
Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
Reviewed-by: default avatarBin Meng <bmeng.cn@gmail.com>
parent e5aa8a9b
......@@ -5,6 +5,7 @@
dtb-y += bayleybay.dtb \
chromebook_link.dtb \
chromebox_panther.dtb \
chromebook_samus.dtb \
cougarcanyon2.dtb \
crownbay.dtb \
efi.dtb \
......
This diff is collapsed.
......@@ -36,9 +36,22 @@ config TARGET_CHROMEBOX_PANTHER
video output and a 16GB SATA solid state drive. There is no Chrome
OS EC on this model.
config TARGET_CHROMEBOOK_SAMUS
bool "Chromebook samus"
help
This is the Chromebook Pixel released in 2015. It uses an Intel
Broadwell U Core i5 or Core i7 CPU with either 8GB or 16GB of
LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
720p webcam, USB SD reader, microphone and speakers, 2 USB 3 Type
C ports which can support charging and up to a 4K external display.
There is a solid state drive, either 32GB or 64GB. There is a
Chrome OS EC connected on LPC, and it provides a 2560x1700 high
resolution touch-enabled LCD display.
endchoice
source "board/google/chromebook_link/Kconfig"
source "board/google/chromebox_panther/Kconfig"
source "board/google/chromebook_samus/Kconfig"
endif
if TARGET_CHROMEBOOK_SAMUS
config SYS_BOARD
default "chromebook_samus"
config SYS_VENDOR
default "google"
config SYS_SOC
default "broadwell"
config SYS_CONFIG_NAME
default "chromebook_samus"
config SYS_TEXT_BASE
default 0xffe00000
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select X86_RESET_VECTOR
select INTEL_BROADWELL
select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
config PCIE_ECAM_BASE
default 0xf0000000
config EARLY_POST_CROS_EC
bool "Enable early post to Chrome OS EC"
default y
config SYS_CAR_ADDR
hex
default 0xff7c0000
config SYS_CAR_SIZE
hex
default 0x40000
endif
CHROMEBOOK SAMUS BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/google/chromebook_samus/
F: include/configs/chromebook_samus.h
F: configs/chromebook_samus_defconfig
#
# Copyright (c) 2016 Google, Inc
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += samus.o
/*
* Copyright (C) 2016 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/cpu.h>
int arch_early_init_r(void)
{
return cpu_run_reference_code();
}
int board_early_init_f(void)
{
return 0;
}
CONFIG_X86=y
CONFIG_SYS_MALLOC_F_LEN=0x1800
CONFIG_VENDOR_GOOGLE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
CONFIG_TARGET_CHROMEBOOK_SAMUS=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_HAVE_MRC=y
CONFIG_HAVE_REFCODE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_INTEL_BROADWELL_GPIO=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_VIDEO=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_VIDEO_BROADWELL_IGD=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y
......@@ -105,6 +105,87 @@ $ make all
---
Chromebook Samus (2015 Pixel) instructions for bare mode:
First, you need the following binary blobs:
* descriptor.bin - Intel flash descriptor
* me.bin - Intel Management Engine
* mrc.bin - Memory Reference Code, which sets up SDRAM
* refcode.elf - Additional Reference code
* vga.bin - video ROM, which sets up the display
If you have a samus you can obtain them from your flash, for example, in
developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
log in as 'root'):
cd /tmp
flashrom -w samus.bin
scp samus.bin username@ip_address:/path/to/somewhere
If not see the coreboot tree [4] where you can use:
bash crosfirmware.sh samus
to get the image. There is also an 'extract_blobs.sh' scripts that you can use
on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
Then 'ifdtool -x samus.bin' on your development machine will produce:
flashregion_0_flashdescriptor.bin
flashregion_1_bios.bin
flashregion_2_intel_me.bin
Rename flashregion_0_flashdescriptor.bin to descriptor.bin
Rename flashregion_2_intel_me.bin to me.bin
You can ignore flashregion_1_bios.bin - it is not used.
To get the rest, use 'cbfstool samus.bin print':
samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
alignment: 64 bytes, architecture: x86
Name Offset Type Size
cmos_layout.bin 0x700000 cmos_layout 1164
pci8086,0406.rom 0x7004c0 optionrom 65536
spd.bin 0x710500 (unknown) 4096
cpu_microcode_blob.bin 0x711540 microcode 70720
fallback/romstage 0x722a00 stage 54210
fallback/ramstage 0x72fe00 stage 96382
config 0x7476c0 raw 6075
fallback/vboot 0x748ec0 stage 15980
fallback/refcode 0x74cd80 stage 75578
fallback/payload 0x75f500 payload 62878
u-boot.dtb 0x76eb00 (unknown) 5318
(empty) 0x770000 null 196504
mrc.bin 0x79ffc0 (unknown) 222876
(empty) 0x7d66c0 null 167320
You can extract what you need:
cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
cbfstool samus.bin extract -n mrc.bin -f mrc.bin
cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
Note that the -U flag is only supported by the latest cbfstool. It unpacks
and decompresses the stage to produce a coreboot rmodule. This is a simple
representation of an ELF file. You need the patch "Support decoding a stage
with compression".
Put all 5 files into board/google/chromebook_samus.
Now you can build U-Boot and obtain u-boot.rom:
$ make chromebook_link_defconfig
$ make all
If you are using em100, then this command will flash write -Boot:
em100 -s -d filename.rom -c W25Q64CV -r
---
Intel Crown Bay specific instructions for bare mode:
U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
......
/*
* Copyright (c) 2011 The Chromium OS Authors.
* (C) Copyright 2008
* Graeme Russ, graeme.russ@gmail.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <configs/x86-common.h>
#include <configs/x86-chromebook.h>
#undef CONFIG_CFB_CONSOLE
#undef CONFIG_STD_DEVICES_SETTINGS
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
"stdout=vidconsole,serial\0" \
"stderr=vidconsole,serial\0"
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x003f8000
#endif /* __CONFIG_H */
......@@ -21,7 +21,8 @@
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
#define CONFIG_PCI_MEM_BUS 0xe0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
......
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