Commit 380dd20f authored by Teo Hall's avatar Teo Hall

MLK-17119 i.MX8QM DDR4 ARM2 Support

Add support for DDR4 board in u-boot.
Main changes are the SD card slot and ddr
type
Signed-off-by: 's avatarTeo Hall <teo.hall@nxp.com>
parent 0bafbeec
......@@ -391,6 +391,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
fsl-imx8mq-ddr4-arm2.dtb
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qm-lpddr4-arm2.dtb \
fsl-imx8qm-ddr4-arm2.dtb \
fsl-imx8qm-mek.dtb \
fsl-imx8qxp-lpddr4-arm2.dtb \
fsl-imx8qxp-mek.dtb
......
This diff is collapsed.
......@@ -102,8 +102,8 @@ int board_early_init_f(void)
static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
{USDHC1_BASE_ADDR, 0, 8},
#endif
{USDHC2_BASE_ADDR, 0, 4},
#endif
{USDHC3_BASE_ADDR, 0, 4},
};
......@@ -122,8 +122,6 @@ static iomux_cfg_t emmc0[] = {
SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
};
#endif
static iomux_cfg_t usdhc1_sd[] = {
SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
......@@ -136,7 +134,7 @@ static iomux_cfg_t usdhc1_sd[] = {
SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
};
#endif
static iomux_cfg_t usdhc2_sd[] = {
SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
......@@ -173,9 +171,6 @@ int board_mmc_init(bd_t *bis)
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
case 1:
#else
case 0:
#endif
if (!power_domain_lookup_name("conn_sdhc1", &pd))
power_domain_on(&pd);
......@@ -185,11 +180,11 @@ int board_mmc_init(bd_t *bis)
gpio_request(USDHC1_CD_GPIO, "sd1_cd");
gpio_direction_input(USDHC1_CD_GPIO);
break;
#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
case 2:
#else
case 1:
case 0:
#endif
if (!power_domain_lookup_name("conn_sdhc2", &pd))
power_domain_on(&pd);
......@@ -221,7 +216,11 @@ int board_mmc_getcd(struct mmc *mmc)
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
ret = 1; /* eMMC */
#else
ret = 0; /* eMMC not present on DDR4 board */
#endif
break;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
......@@ -553,7 +552,7 @@ int board_mmc_get_env_dev(int devno)
#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
return devno;
#else
return devno - 1;
return devno - 2;
#endif
}
......@@ -562,7 +561,7 @@ int mmc_map_to_kernel_blk(int dev_no)
#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
return dev_no;
#else
return dev_no + 1;
return dev_no + 2;
#endif
}
......
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-ddr4-arm2"
CONFIG_TARGET_IMX8QM_DDR4_ARM2=y
CONFIG_CMD_IMPORTENV=n
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM=y
CONFIG_CMD_CACHE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_OF_CONTROL=y
CONFIG_DM_I2C=y
# CONFIG_DM_I2C_COMPAT is not set
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_CMD_I2C=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_IMX8=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_CMD_GPIO=y
CONFIG_DM_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_BOOTDELAY=3
CONFIG_IMX_BOOTAUX=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MMC=y
CONFIG_DM_MMC=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_FSL_FSPI=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_4BYTES_ADDR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_SF=y
CONFIG_CMD_PING=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_DM_ETH=y
# CONFIG_EFI_LOADER is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_VIDEO=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8_POWER_DOMAIN=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_SC_THERMAL=y
......@@ -31,7 +31,9 @@
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define USDHC3_BASE_ADDR 0x5B030000
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#endif
#define CONFIG_ENV_OVERWRITE
......@@ -135,7 +137,7 @@
"fdt_addr=0x83000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fdt=try\0" \
"fdt_file=fsl-imx8qm-lpddr4-arm2.dtb\0" \
"fdt_file="__stringify(CONFIG_DEFAULT_DEVICE_TREE)".dtb\0" \
"initrd_addr=0x83800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
......@@ -226,13 +228,16 @@
* On DDR4 board, USDHC1 is mux for NAND, USDHC2 is for SD, USDHC3 is for SD on base board
*/
#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC1 */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC1 */
#define CONFIG_SYS_FSL_USDHC_NUM 3
#else
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 1
#endif
/* Size of malloc() pool */
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment