Commit 384980c6 authored by Bin Meng's avatar Bin Meng

dm: pch: Add get_gpio_base op

x86 GPIO registers are accessed via I/O port whose base address is
configured in a PCI configuration register on the PCH device. Add
an op get_gpio_base to get the GPIO base address from PCH.
Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
Tested-by: default avatarSimon Glass <sjg@chromium.org>
parent 3e389d8b
......@@ -33,6 +33,17 @@ int pch_set_spi_protect(struct udevice *dev, bool protect)
return ops->set_spi_protect(dev, protect);
}
int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
{
struct pch_ops *ops = pch_get_ops(dev);
*gbasep = 0;
if (!ops->get_gpio_base)
return -ENOSYS;
return ops->get_gpio_base(dev, gbasep);
}
static int pch_uclass_post_bind(struct udevice *bus)
{
/*
......
......@@ -32,6 +32,15 @@ struct pch_ops {
* @return 0 on success, -ENOSYS if not implemented
*/
int (*set_spi_protect)(struct udevice *dev, bool protect);
/**
* get_gpio_base() - get the address of GPIO base
*
* @dev: PCH device to check
* @gbasep: Returns address of GPIO base if available, else 0
* @return 0 if OK, -ve on error (e.g. there is no GPIO base)
*/
int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
};
#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
......@@ -55,4 +64,13 @@ int pch_get_spi_base(struct udevice *dev, ulong *sbasep);
*/
int pch_set_spi_protect(struct udevice *dev, bool protect);
/**
* pch_get_gpio_base() - get the address of GPIO base
*
* @dev: PCH device to check
* @gbasep: Returns address of GPIO base if available, else 0
* @return 0 if OK, -ve on error (e.g. there is no GPIO base)
*/
int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
#endif
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