Commit 39da644e authored by Stuart Yoder's avatar Stuart Yoder Committed by York Sun

armv8/fsl-lsch3: partition stream IDs

Stream IDs on ls2085a devices are not hardwired and are
programmed by sw.  There are a limited number of stream IDs
available, and the partitioning of them is scenario dependent.
This header defines the partitioning between legacy, PCI,
and DPAA2 devices.
Signed-off-by: default avatarStuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
parent 2b7c4a19
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
*/
#ifndef __FSL_STREAM_ID_H
#define __FSL_STREAM_ID_H
/* Stream IDs on ls2085a devices are not hardwired and are
* programmed by sw. There are a limited number of stream IDs
* available, and the partitioning of them is scenario dependent.
* This header defines the partitioning between legacy, PCI,
* and DPAA2 devices.
*
* This partitiong can be customized in this file depending
* on the specific hardware config-- e.g. perhaps not all
* PEX controllers are in use.
*
* On LS2085 stream IDs are programmed in AMQ registers (32-bits) for
* each of the different bus masters. The relationship between
* the AMQ registers and stream IDs is defined in the table below:
* AMQ bit streamID bit
* ---------------------------
* PL[18] 9
* BMT[17] 8
* VA[16] 7
* [15] -
* ICID[14:7] -
* ICID[6:0] 6-0
* ----------------------------
*/
#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
#define FSL_INVALID_STREAM_ID 0
#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
/* legacy devices */
#define FSL_USB1_STREAM_ID 1
#define FSL_USB2_STREAM_ID 2
#define FSL_SDMMC_STREAM_ID 3
#define FSL_SATA1_STREAM_ID 4
#define FSL_SATA2_STREAM_ID 5
#define FSL_DMA_STREAM_ID 6
/* PCI - programmed in PEXn_LUT by OS */
/* 4 IDs per controller */
#define FSL_PEX1_STREAM_ID_START 7
#define FSL_PEX1_STREAM_ID_END 10
#define FSL_PEX2_STREAM_ID_START 11
#define FSL_PEX2_STREAM_ID_END 14
#define FSL_PEX3_STREAM_ID_START 15
#define FSL_PEX3_STREAM_ID_END 18
#define FSL_PEX4_STREAM_ID_START 19
#define FSL_PEX4_STREAM_ID_END 22
/* DPAA2 - set in MC DPC and alloced by MC */
#define FSL_DPAA2_STREAM_ID_START 23
#define FSL_DPAA2_STREAM_ID_END 63
#endif
......@@ -474,7 +474,7 @@ int mc_init(void)
out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
out_le32(&mc_ccsr_regs->reg_mcfbahr,
(u32)(mc_ram_aligned_base_addr >> 32));
out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK);
out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ);
/*
* Tell the MC that we want delayed DPL deployment.
......
......@@ -19,6 +19,7 @@
#define CONFIG_ARM_ERRATA_828024
#define CONFIG_ARM_ERRATA_826974
#include <asm/arch-fsl-lsch3/ls2085a_stream_id.h>
#include <asm/arch-fsl-lsch3/config.h>
#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
#define CONFIG_SYS_HAS_SERDES
......
......@@ -21,10 +21,6 @@
#define GCR1_M2_DE_RST BIT(14)
#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST)
#define GSR_FS_MASK 0x3fffffff
#define MCFAPR_PL_MASK (0x1 << 18)
#define MCFAPR_BMT_MASK (0x1 << 17)
#define MCFAPR_BYPASS_ICID_MASK \
(MCFAPR_PL_MASK | MCFAPR_BMT_MASK)
#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000)
#define SOC_QBMAN_PORTALS_BASE_ADDR ((void __iomem *)0x000818000000)
......
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