Commit 3cba1c7d authored by Ye Li's avatar Ye Li Committed by Jason Liu

MLK-14970-4 imx8qxp_arm2: Add i.MX8QXP ARM2 board support

Add board level codes and DTS for i.MX8QXP LPDDR4 ARM2 board.

Copy the DTS from imx_4.9.y kernel on commit:
"4590bca4a6bc6ae8625c37bb027697a17d1b925f"
With modifications to support FlexSPI flash, PCA953x and MIPI I2C.

- Enabled DM driver:
  FEC, LPUART, LPI2C, GPIO, SD/MMC, FSPI, PCA953X

- Enabled Non-DM driver:
  PCIE, iomux, fuse

- Disabled driver:
  mailbox, pinctrl (will try to use later)

- Board defconfigs:
  imx8qxp_lpddr4_arm2_defconfig
Signed-off-by: 's avatarRanjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Signed-off-by: 's avatarFugang Duan <fugang.duan@nxp.com>
Signed-off-by: 's avatarHan Xu <han.xu@nxp.com>
Signed-off-by: 's avatarPrabhu Sundararaj <prabhu.sundararaj@nxp.com>
Signed-off-by: 's avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
parent b8b78854
......@@ -37,8 +37,13 @@ config TARGET_IMX8QM_DDR4_ARM2
bool "Support i.MX8QM ddr4 validation board"
select IMX8QM
config TARGET_IMX8QXP_LPDDR4_ARM2
bool "Support i.MX8QXP lpddr4 validation board"
select IMX8QXP
endchoice
source "board/freescale/imx8qm_arm2/Kconfig"
source "board/freescale/imx8qxp_arm2/Kconfig"
endif
......@@ -386,7 +386,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb \
imx7ulp-10x10-arm2.dtb \
imx7ulp-14x14-arm2.dtb
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qm-lpddr4-arm2.dtb
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qm-lpddr4-arm2.dtb \
fsl-imx8qxp-lpddr4-arm2.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
......
/*
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
/* First 128KB is for PSCI ATF. */
/* Last 3M is for M4/RPMSG */
/memreserve/ 0x80000000 0x00400000;
#include "fsl-imx8qxp.dtsi"
/ {
model = "Freescale i.MX8QXP LPDDR4 ARM2";
compatible = "fsl,imx8qxp-lpddr4-arm2", "fsl,imx8qxp";
chosen {
bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
stdout-path = &lpuart0;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_sd1_vmmc: sd1_vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
};
&iomuxc {
imx8qxp-arm2 {
pinctrl_fec1: fec1grp {
fsl,pins = <
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048
SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048
SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048
SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048
SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000048
SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000048
SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000048
SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000048
SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000048
SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000048
SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000048
SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000048
SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000048
SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000048
SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000048
SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000048
>;
};
pinctrl_lpi2c1: lpi1cgrp {
fsl,pins = <
SC_P_USB_SS3_TC0_ADMA_I2C1_SCL 0x06000020
SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000020
>;
};
pinctrl_lpi2c3: lpi2cgrp {
fsl,pins = <
SC_P_SPI3_CS1_ADMA_I2C3_SCL 0x06000020
SC_P_MCLK_IN1_ADMA_I2C3_SDA 0x06000020
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX_ADMA_UART0_RX 0x0600004c
SC_P_UART0_TX_ADMA_UART0_TX 0x0600004c
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000021
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc2_rst: usdhc2_rst_grp {
fsl,pins = <
SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x06000048
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000021
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000021
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000021
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000021
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021
SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x06000021
SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c
SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c
SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c
SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c
SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c
SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c
SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c
SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c
SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c
SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c
SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c
SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c
SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c
SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c
SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c
>;
};
};
};
&gpio0 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&gpio4 {
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
fsl,ar8031-phy-fixup;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
fsl,ar8031-phy-fixup;
fsl,magic-packet;
status = "disabled";
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: mt35xu512aba@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <8>;
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c1>;
status = "okay";
};
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c3>;
status = "okay";
pca9557_a: gpio@18 {
compatible = "nxp,pca9557";
reg = <0x18>;
gpio-controller;
#gpio-cells = <2>;
};
pca9557_b: gpio@19 {
compatible = "nxp,pca9557";
reg = <0x19>;
gpio-controller;
#gpio-cells = <2>;
};
pca9557_c: gpio@1b {
compatible = "nxp,pca9557";
reg = <0x1b>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c0_mipi0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
clock-frequency = <100000>;
status = "okay";
it6263-0@4c {
compatible = "ITE,it6263";
reg = <0x4c>;
};
};
&i2c0_mipi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
clock-frequency = <100000>;
status = "okay";
it6263-1@4c {
compatible = "ITE,it6263";
reg = <0x4c>;
};
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_rst>;
bus-width = <4>;
cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_sd1_vmmc>;
status = "okay";
};
if TARGET_IMX8QXP_LPDDR4_ARM2
config SYS_BOARD
default "imx8qxp_arm2"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "imx8qxp_arm2"
endif
#
# Copyright 2017 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx8qxp_arm2.o
This diff is collapsed.
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-arm2"
CONFIG_TARGET_IMX8QXP_LPDDR4_ARM2=y
CONFIG_CMD_IMPORTENV=n
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_OF_CONTROL=y
CONFIG_DM_I2C=y
# CONFIG_DM_I2C_COMPAT is not set
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_USB is not set
# CONFIG_USB is not set
CONFIG_CMD_GPIO=y
CONFIG_DM_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_BOOTDELAY=3
CONFIG_IMX_BOOTAUX=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MMC=y
CONFIG_DM_MMC=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_FSL_FSPI=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_SF=y
CONFIG_CMD_PING=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_DM_ETH=y
# CONFIG_EFI_LOADER is not set
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMX8QXP_ARM2_H
#define __IMX8QXP_ARM2_H
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
#define CONFIG_REMAKE_ELF
#define CONFIG_BOARD_EARLY_INIT_F
/* Flat Device Tree Definitions */
#define CONFIG_OF_BOARD_SETUP
#undef CONFIG_CMD_EXPORTENV
#undef CONFIG_CMD_IMPORTENV
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_CRC32
#undef CONFIG_BOOTM_NETBSD
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_HSIO
#ifdef CONFIG_FSL_HSIO
#define CONFIG_PCIE_IMX8X
#define CONFIG_CMD_PCI
#define CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI_ENUM
#endif
/* FUSE command */
#define CONFIG_CMD_FUSE
/* GPIO configs */
#define CONFIG_MXC_GPIO
/* ENET Config */
#define CONFIG_MII
#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define FEC_QUIRK_ENET_MAC
#define CONFIG_PHY_GIGE /* Support for 1000BASE-X */
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board and MUX with ESAI, default is ESAI */
#define CONFIG_FEC_ENET_DEV 0
#if (CONFIG_FEC_ENET_DEV == 0)
#define IMX_FEC_BASE 0x5B040000
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CONFIG_ETHPRIME "eth0"
#elif (CONFIG_FEC_ENET_DEV == 1)
#define IMX_FEC_BASE 0x5B050000
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_FEC_ENABLE_MAX7322
#define CONFIG_ETHPRIME "eth1"
#endif
/* ENET0 MDIO are shared */
#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000
/* MAX7322 */
#ifdef CONFIG_FEC_ENABLE_MAX7322
#define CONFIG_MAX7322_I2C_ADDR 0x68
#define CONFIG_MAX7322_I2C_BUS 0 /* I2C1 */
#endif
/* Boot M4 */
#define M4_BOOT_ENV \
"m4_0_image=m4_0.bin\0" \
"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
"m4boot_0=run loadm4image_0; bootaux ${loadaddr} 0\0" \
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
M4_BOOT_ENV \
"script=boot.scr\0" \
"image=Image\0" \
"mmcdev=1\0"\
"console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200\0" \
"fdtaddr=0x83000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fdt=try\0" \
"fdt_file=fsl-imx8qxp-lpddr4-arm2.dtb\0" \
"initrd_addr=0x83800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} " \
"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"booti ${loadaddr} - ${fdtaddr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"else " \
"echo wait for boot; " \
"fi;\0" \
"netargs=setenv bootargs console=${console} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
"video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${loadaddr} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdtaddr} ${fdt_file}; then " \
"booti ${loadaddr} - ${fdtaddr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"else " \
"booti; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"else booti ${loadaddr} - ${fdtaddr}; " \
"fi; " \
"fi; " \
"else booti ${loadaddr} - ${fdtaddr}; fi"
/* Link Definitions */
#define CONFIG_LOADADDR 0x80080000
#define CONFIG_SYS_TEXT_BASE 0x80020000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_SP_ADDR 0x90000000
/* Default environment is in SD */
#define CONFIG_ENV_OFFSET (14 * SZ_64K)
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board
*/
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 2
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (16*1024)) * 1024)
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
/* LPDDR4 board total DDR is 3GB */
#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
/* Serial */
#define CONFIG_BAUDRATE 115200
/* Monitor Command Prompt */
#define CONFIG_SYS_LONGHELP
#define CONFIG_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_CMDLINE_EDITING
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
#ifndef CONFIG_DM_PCA953X
#define CONFIG_PCA953X
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#endif
#define CONFIG_IMX_SMMU
/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */
#ifdef CONFIG_FSL_FSPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define FSL_FSPI_FLASH_SIZE SZ_64M
#define FSL_FSPI_FLASH_NUM 1
#define FSPI0_BASE_ADDR 0x5d120000
#define FSPI0_AMBA_BASE 0
#define CONFIG_SYS_FSL_FSPI_AHB
#endif
#endif /* __IMX8QXP_ARM2_H */
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