Commit 3f353cec authored by Albert ARIBAUD \\(3ADEV\\)'s avatar Albert ARIBAUD \\(3ADEV\\) Committed by Stefano Babic

vf610: refactor DDRMC code

The VF610 DDRMC driver code contains settings which are
board-specific. Move these out to boards so that new boards
can define their own without having to modify the driver.
Signed-off-by: 's avatarAlbert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
parent b9a16099
This diff is collapsed.
......@@ -11,18 +11,6 @@
#ifndef __ASM_ARCH_VF610_DDRMC_H
#define __ASM_ARCH_VF610_DDRMC_H
struct ddrmc_lvl_info {
u16 wrlvl_reg_en;
u16 wrlvl_dl_0;
u16 wrlvl_dl_1;
u16 rdlvl_gt_reg_en;
u16 rdlvl_gt_dl_0;
u16 rdlvl_gt_dl_1;
u16 rdlvl_reg_en;
u16 rdlvl_dl_0;
u16 rdlvl_dl_1;
};
struct ddr3_jedec_timings {
u8 tinit;
u32 trst_pwron;
......@@ -32,6 +20,7 @@ struct ddr3_jedec_timings {
u8 trc;
u8 trrd;
u8 tccd;
u8 tbst_int_interval;
u8 tfaw;
u8 trp;
u8 twtr;
......@@ -43,30 +32,51 @@ struct ddr3_jedec_timings {
u8 tckesr;
u8 tcke;
u8 trcd_int;
u8 tras_lockout;
u8 tdal;
u8 bstlen;
u16 tdll;
u8 trp_ab;
u16 tref;
u8 trfc;
u16 tref_int;
u8 tpdex;
u8 txpdll;
u8 txsnr;
u16 txsr;
u8 cksrx;
u8 cksre;
u8 freq_chg_en;
u16 zqcl;
u16 zqinit;
u8 zqcs;
u8 ref_per_zq;
u8 zqcs_rotate;
u8 aprebit;
u8 cmd_age_cnt;
u8 age_cnt;
u8 q_fullness;
u8 odt_rd_mapcs0;
u8 odt_wr_mapcs0;
u8 wlmrd;
u8 wldqsen;
};
void ddrmc_setup_iomux(void);
struct ddrmc_cr_setting {
u32 setting;
int cr_rnum; /* CR register ; -1 for last entry */
};
struct ddrmc_phy_setting {
u32 setting;
int phy_rnum; /* PHY register ; -1 for last entry */
};
void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count);
void ddrmc_phy_init(void);
void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
struct ddrmc_lvl_info *lvl,
int col_diff, int row_diff);
struct ddrmc_cr_setting *board_cr_settings,
struct ddrmc_phy_setting *board_phy_settings,
int col_diff, int row_diff);
#endif
......@@ -148,7 +148,7 @@
#define DDRMC_CR18_TCKE(v) ((v) & 0x7)
#define DDRMC_CR20_AP_EN (1 << 24)
#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16)
#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8)
#define DDRMC_CR21_TRAS_LOCKOUT(v) ((v) << 8)
#define DDRMC_CR21_CCMAP_EN 1
#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16)
#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24)
......@@ -200,8 +200,8 @@
#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24)
#define DDRMC_CR82_INT_MASK 0x10000000
#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24)
#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16)
#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24)
#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16)
#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
......
......@@ -28,63 +28,117 @@ DECLARE_GLOBAL_DATA_PTR;
#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
static struct ddrmc_cr_setting vf610twr_cr_settings[] = {
/* levelling */
{ DDRMC_CR97_WRLVL_EN, 97 },
{ DDRMC_CR98_WRLVL_DL_0(0), 98 },
{ DDRMC_CR99_WRLVL_DL_1(0), 99 },
{ DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
{ DDRMC_CR105_RDLVL_DL_0(0), 105 },
{ DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
{ DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
/* AXI */
{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
{ DDRMC_CR120_AXI0_PRI1_RPRI(2) |
DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
{ DDRMC_CR121_AXI0_PRI3_RPRI(2) |
DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
{ DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
DDRMC_CR122_AXI0_PRIRLX(100), 122 },
{ DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
{ DDRMC_CR124_AXI1_PRIRLX(100), 124 },
{ DDRMC_CR126_PHY_RDLAT(8), 126 },
{ DDRMC_CR132_WRLAT_ADJ(5) |
DDRMC_CR132_RDLAT_ADJ(6), 132 },
{ DDRMC_CR137_PHYCTL_DL(2), 137 },
{ DDRMC_CR138_PHY_WRLV_MXDL(256) |
DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
{ DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
DDRMC_CR139_PHY_WRLV_DLL(3) |
DDRMC_CR139_PHY_WRLV_EN(3), 139 },
{ DDRMC_CR140_PHY_WRLV_WW(64), 140 },
{ DDRMC_CR143_RDLV_GAT_MXDL(1536) |
DDRMC_CR143_RDLV_MXDL(128), 143 },
{ DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
DDRMC_CR144_PHY_RDLV_DLL(3) |
DDRMC_CR144_PHY_RDLV_EN(3), 144 },
{ DDRMC_CR145_PHY_RDLV_RR(64), 145 },
{ DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
{ DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
{ DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
{ DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
{ DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
DDRMC_CR154_PAD_ZQ_MODE(1) |
DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
{ DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
{ DDRMC_CR158_TWR(6), 158 },
{ DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
DDRMC_CR161_TODTH_WR(2), 161 },
/* end marker */
{ 0, -1 }
};
int dram_init(void)
{
struct ddrmc_lvl_info lvl = {
.wrlvl_reg_en = 1,
.wrlvl_dl_0 = 0,
.wrlvl_dl_1 = 0,
.rdlvl_gt_reg_en = 1,
.rdlvl_gt_dl_0 = 4,
.rdlvl_gt_dl_1 = 4,
.rdlvl_reg_en = 1,
.rdlvl_dl_0 = 0,
.rdlvl_dl_1 = 0,
};
static const struct ddr3_jedec_timings timings = {
.tinit = 5,
.trst_pwron = 80000,
.cke_inactive = 200000,
.wrlat = 5,
.caslat_lin = 12,
.trc = 21,
.trrd = 4,
.tccd = 4,
.tfaw = 20,
.trp = 6,
.twtr = 4,
.tras_min = 15,
.tmrd = 4,
.trtp = 4,
.tras_max = 28080,
.tmod = 12,
.tckesr = 4,
.tcke = 3,
.trcd_int = 6,
.tdal = 12,
.tdll = 512,
.trp_ab = 6,
.tref = 3120,
.trfc = 44,
.tpdex = 3,
.txpdll = 10,
.txsnr = 48,
.txsr = 468,
.cksrx = 5,
.cksre = 5,
.zqcl = 256,
.zqinit = 512,
.zqcs = 64,
.ref_per_zq = 64,
.aprebit = 10,
.wlmrd = 40,
.wldqsen = 25,
.tinit = 5,
.trst_pwron = 80000,
.cke_inactive = 200000,
.wrlat = 5,
.caslat_lin = 12,
.trc = 21,
.trrd = 4,
.tccd = 4,
.tbst_int_interval = 0,
.tfaw = 20,
.trp = 6,
.twtr = 4,
.tras_min = 15,
.tmrd = 4,
.trtp = 4,
.tras_max = 28080,
.tmod = 12,
.tckesr = 4,
.tcke = 3,
.trcd_int = 6,
.tras_lockout = 0,
.tdal = 12,
.bstlen = 0,
.tdll = 512,
.trp_ab = 6,
.tref = 3120,
.trfc = 44,
.tref_int = 0,
.tpdex = 3,
.txpdll = 10,
.txsnr = 48,
.txsr = 468,
.cksrx = 5,
.cksre = 5,
.freq_chg_en = 0,
.zqcl = 256,
.zqinit = 512,
.zqcs = 64,
.ref_per_zq = 64,
.zqcs_rotate = 0,
.aprebit = 10,
.cmd_age_cnt = 64,
.age_cnt = 64,
.q_fullness = 7,
.odt_rd_mapcs0 = 0,
.odt_wr_mapcs0 = 1,
.wlmrd = 40,
.wldqsen = 25,
};
ddrmc_setup_iomux();
ddrmc_setup_iomux(NULL, 0);
ddrmc_ctrl_init_ddr3(&timings, &lvl, 1, 3);
ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3);
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
......
......@@ -35,6 +35,61 @@ DECLARE_GLOBAL_DATA_PTR;
#define USB_PEN_GPIO 83
static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
/* levelling */
{ DDRMC_CR97_WRLVL_EN, 97 },
{ DDRMC_CR98_WRLVL_DL_0(0), 98 },
{ DDRMC_CR99_WRLVL_DL_1(0), 99 },
{ DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
{ DDRMC_CR105_RDLVL_DL_0(0), 105 },
{ DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
{ DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
/* AXI */
{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
{ DDRMC_CR120_AXI0_PRI1_RPRI(2) |
DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
{ DDRMC_CR121_AXI0_PRI3_RPRI(2) |
DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
{ DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
DDRMC_CR122_AXI0_PRIRLX(100), 122 },
{ DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
{ DDRMC_CR124_AXI1_PRIRLX(100), 124 },
{ DDRMC_CR126_PHY_RDLAT(8), 126 },
{ DDRMC_CR132_WRLAT_ADJ(5) |
DDRMC_CR132_RDLAT_ADJ(6), 132 },
{ DDRMC_CR137_PHYCTL_DL(2), 137 },
{ DDRMC_CR138_PHY_WRLV_MXDL(256) |
DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
{ DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
DDRMC_CR139_PHY_WRLV_DLL(3) |
DDRMC_CR139_PHY_WRLV_EN(3), 139 },
{ DDRMC_CR140_PHY_WRLV_WW(64), 140 },
{ DDRMC_CR143_RDLV_GAT_MXDL(1536) |
DDRMC_CR143_RDLV_MXDL(128), 143 },
{ DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
DDRMC_CR144_PHY_RDLV_DLL(3) |
DDRMC_CR144_PHY_RDLV_EN(3), 144 },
{ DDRMC_CR145_PHY_RDLV_RR(64), 145 },
{ DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
{ DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
{ DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
{ DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
{ DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
DDRMC_CR154_PAD_ZQ_MODE(1) |
DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
{ DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
{ DDRMC_CR158_TWR(6), 158 },
{ DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
DDRMC_CR161_TODTH_WR(2), 161 },
/* end marker */
{ 0, -1 }
};
static const iomux_v3_cfg_t usb_pads[] = {
VF610_PAD_PTD4__GPIO_83,
};
......@@ -42,48 +97,59 @@ static const iomux_v3_cfg_t usb_pads[] = {
int dram_init(void)
{
static const struct ddr3_jedec_timings timings = {
.tinit = 5,
.trst_pwron = 80000,
.cke_inactive = 200000,
.wrlat = 5,
.caslat_lin = 12,
.trc = 21,
.trrd = 4,
.tccd = 4,
.tfaw = 20,
.trp = 6,
.twtr = 4,
.tras_min = 15,
.tmrd = 4,
.trtp = 4,
.tras_max = 28080,
.tmod = 12,
.tckesr = 4,
.tcke = 3,
.trcd_int = 6,
.tdal = 12,
.tdll = 512,
.trp_ab = 6,
.tref = 3120,
.trfc = 64,
.tpdex = 3,
.txpdll = 10,
.txsnr = 48,
.txsr = 468,
.cksrx = 5,
.cksre = 5,
.zqcl = 256,
.zqinit = 512,
.zqcs = 64,
.ref_per_zq = 64,
.aprebit = 10,
.wlmrd = 40,
.wldqsen = 25,
.tinit = 5,
.trst_pwron = 80000,
.cke_inactive = 200000,
.wrlat = 5,
.caslat_lin = 12,
.trc = 21,
.trrd = 4,
.tccd = 4,
.tbst_int_interval = 0,
.tfaw = 20,
.trp = 6,
.twtr = 4,
.tras_min = 15,
.tmrd = 4,
.trtp = 4,
.tras_max = 28080,
.tmod = 12,
.tckesr = 4,
.tcke = 3,
.trcd_int = 6,
.tras_lockout = 0,
.tdal = 12,
.bstlen = 0,
.tdll = 512,
.trp_ab = 6,
.tref = 3120,
.trfc = 64,
.tref_int = 0,
.tpdex = 3,
.txpdll = 10,
.txsnr = 48,
.txsr = 468,
.cksrx = 5,
.cksre = 5,
.freq_chg_en = 0,
.zqcl = 256,
.zqinit = 512,
.zqcs = 64,
.ref_per_zq = 64,
.zqcs_rotate = 0,
.aprebit = 10,
.cmd_age_cnt = 64,
.age_cnt = 64,
.q_fullness = 7,
.odt_rd_mapcs0 = 0,
.odt_wr_mapcs0 = 1,
.wlmrd = 40,
.wldqsen = 25,
};
ddrmc_setup_iomux();
ddrmc_setup_iomux(NULL, 0);
ddrmc_ctrl_init_ddr3(&timings, NULL, 1, 2);
ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
......
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