Commit 41cd537c authored by Ye Li's avatar Ye Li Committed by Jason Liu

MLK-16503 imx8qm_mek: Add support for QM MEK board

Add build config, dts and board codes for i.MX8QM MEK board. Supported
peripherals: UART, eMMC/SD, ENET, I2C, USB TYPEC DFP mode, flexspi.

DTS is ported from kernel commit a4fff857ea5f0a6513b943e0b0b842d5008785f1,
and enable more peripherals.
Signed-off-by: 's avatarYe Li <ye.li@nxp.com>
Reviewed-by: 's avatarPeng Fan <peng.fan@nxp.com>
parent 1fad235a
......@@ -39,6 +39,11 @@ config TARGET_IMX8QM_DDR4_ARM2
select BOARD_LATE_INIT
select IMX8QM
config TARGET_IMX8QM_MEK
bool "Support i.MX8QM MEK board"
select BOARD_LATE_INIT
select IMX8QM
config TARGET_IMX8QXP_LPDDR4_ARM2
bool "Support i.MX8QXP lpddr4 validation board"
select BOARD_LATE_INIT
......@@ -52,6 +57,7 @@ config TARGET_IMX8QXP_MEK
endchoice
source "board/freescale/imx8qm_arm2/Kconfig"
source "board/freescale/imx8qm_mek/Kconfig"
source "board/freescale/imx8qxp_arm2/Kconfig"
source "board/freescale/imx8qxp_mek/Kconfig"
......
......@@ -389,6 +389,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb \
dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qm-lpddr4-arm2.dtb \
fsl-imx8qm-mek.dtb \
fsl-imx8qxp-lpddr4-arm2.dtb \
fsl-imx8qxp-mek.dtb
......
/*
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "fsl-imx8qm.dtsi"
/ {
model = "Freescale i.MX8QM MEK";
compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
chosen {
bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
stdout-path = &lpuart0;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usdhc2_vmmc: usdhc2_vmmc {
compatible = "regulator-fixed";
regulator-name = "sw-3p3-sd1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1>;
imx8qm-mek {
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x06000021
SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x06000021
SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x06000021
SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x06000021
SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x06000021
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048
SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048
SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048
SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048
SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048
SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000048
SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000048
SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000048
SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000048
SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000048
SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000048
SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048
SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000048
SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000048
SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000048
SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000048
>;
};
pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
fsl,pins = <
SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c
SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c
>;
};
pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
fsl,pins = <
SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c
SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX_DMA_UART0_RX 0x06000020
SC_P_UART0_TX_DMA_UART0_TX 0x06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
>;
};
pinctrl_lpi2c0: lpi2c0grp {
fsl,pins = <
SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000020
SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000020
>;
};
pinctrl_lpspi0: lpspi0grp {
fsl,pins = <
SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c
SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c
SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c
SC_P_SPI0_CS0_DMA_SPI0_CS0 0x0600004c
SC_P_SPI0_CS1_DMA_SPI0_CS1 0x0600004c
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c
SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c
SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c
SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c
SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c
SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c
SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c
SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c
SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c
SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c
SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c
SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c
SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c
SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c
SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c
>;
};
};
};
&gpio2 {
status = "okay";
};
&gpio4 {
status = "okay";
};
&gpio5 {
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usb2 {
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
fsl,magic-packet;
fsl,rgmii_txc_dly;
fsl,rgmii_rxc_dly;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
fsl,ar8031-phy-fixup;
fsl,magic-packet;
status = "okay";
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: mt35xu512aba@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <8>;
};
};
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c0>;
status = "okay";
};
&i2c1_lvds0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
clock-frequency = <100000>;
status = "okay";
it6263-0@4c {
compatible = "ITE,it6263";
reg = <0x4c>;
};
};
&i2c1_lvds1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
clock-frequency = <100000>;
status = "okay";
it6263-1@4c {
compatible = "ITE,it6263";
reg = <0x4c>;
};
};
&lpspi0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi0>;
status = "okay";
spidev0: spi@0 {
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <4000000>;
};
};
&lpuart0 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
if TARGET_IMX8QM_MEK
config SYS_BOARD
default "imx8qm_mek"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "imx8qm_mek"
endif
#
# Copyright 2017 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx8qm_mek.o
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fdt_support.h>
#include <libfdt.h>
#include <environment.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/imx-common/sci/sci.h>
#include <asm/arch/imx8-pins.h>
#include <dm.h>
#include <imx8_hsio.h>
#include <usb.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/video.h>
#include <asm/arch/video_common.h>
#include <power-domain.h>
#include "../common/tcpc.h"
DECLARE_GLOBAL_DATA_PTR;
#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
| (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
static iomux_cfg_t uart0_pads[] = {
SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
}
int board_early_init_f(void)
{
sc_ipc_t ipcHndl = 0;
sc_err_t sciErr = 0;
ipcHndl = gd->arch.ipc_channel_handle;
/* Power up UART0, this is very early while power domain is not working */
sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_UART_0, SC_PM_PW_MODE_ON);
if (sciErr != SC_ERR_NONE)
return 0;
/* Set UART0 clock root to 80 MHz */
sc_pm_clock_rate_t rate = 80000000;
sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_0, 2, &rate);
if (sciErr != SC_ERR_NONE)
return 0;
/* Enable UART0 clock root */
sciErr = sc_pm_clock_enable(ipcHndl, SC_R_UART_0, 2, true, false);
if (sciErr != SC_ERR_NONE)
return 0;
setup_iomux_uart();
return 0;
}
#ifdef CONFIG_FEC_MXC
#include <miiphy.h>
static iomux_cfg_t pad_enet1[] = {
SC_P_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET1_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET1_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET1_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET1_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET1_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET1_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET1_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET1_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
/* Shared MDIO */
SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
};
static iomux_cfg_t pad_enet0[] = {
SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
/* Shared MDIO */
SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
};
static void setup_iomux_fec(void)
{
if (0 == CONFIG_FEC_ENET_DEV)
imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
else
imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1));
}
int board_eth_init(bd_t *bis)
{
int ret;
struct power_domain pd;
printf("[%s] %d\n", __func__, __LINE__);
if (CONFIG_FEC_ENET_DEV) {
if (!power_domain_lookup_name("conn_enet1", &pd))
power_domain_on(&pd);
} else {
if (!power_domain_lookup_name("conn_enet0", &pd))
power_domain_on(&pd);
}
setup_iomux_fec();
ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
if (ret)
printf("FEC1 MXC: %s:failed\n", __func__);
return ret;
}
int board_phy_config(struct phy_device *phydev)
{
#ifdef CONFIG_FEC_ENABLE_MAX7322
uint8_t value;
/* This is needed to drive the pads to 1.8V instead of 1.5V */
i2c_set_bus_num(CONFIG_MAX7322_I2C_BUS);
if (!i2c_probe(CONFIG_MAX7322_I2C_ADDR)) {
/* Write 0x1 to enable O0 output, this device has no addr */
/* hence addr length is 0 */
value = 0x1;
if (i2c_write(CONFIG_MAX7322_I2C_ADDR, 0, 0, &value, 1))
printf("MAX7322 write failed\n");
} else {
printf("MAX7322 Not found\n");
}
mdelay(1);
#endif
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
#ifdef CONFIG_MXC_GPIO
#define LVDS_ENABLE IMX_GPIO_NR(1, 6)
#define MIPI_ENABLE IMX_GPIO_NR(1, 7)
#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20)
#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24)
#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23)
static void board_gpio_init(void)
{
/* Enable BB 3V3 */
gpio_request(BB_GPIO_3V3_1, "bb_3v3_1");
gpio_direction_output(BB_GPIO_3V3_1, 1);
gpio_request(BB_GPIO_3V3_2, "bb_3v3_2");
gpio_direction_output(BB_GPIO_3V3_2, 1);
gpio_request(BB_GPIO_3V3_3, "bb_3v3_3");
gpio_direction_output(BB_GPIO_3V3_3, 1);
/* enable LVDS SAS boards */
gpio_request(LVDS_ENABLE, "lvds_enable");
gpio_direction_output(LVDS_ENABLE, 1);
/* enable MIPI SAS boards */
gpio_request(MIPI_ENABLE, "mipi_enable");
gpio_direction_output(MIPI_ENABLE, 1);
}
#endif
int checkboard(void)
{
puts("Board: iMX8QM MEK\n");
print_bootinfo();
/* Note: After reloc, ipcHndl will no longer be valid. If handle
* returned by sc_ipc_open matches SC_IPC_CH, use this
* macro (valid after reloc) for subsequent SCI calls.
*/
if (gd->arch.ipc_channel_handle != SC_IPC_CH) {
printf("\nSCI error! Invalid handle\n");
}
#ifdef SCI_FORCE_ABORT
sc_rpc_msg_t abort_msg;
puts("Send abort request\n");
RPC_SIZE(&abort_msg) = 1;
RPC_SVC(&abort_msg) = SC_RPC_SVC_ABORT;
sc_ipc_write(SC_IPC_CH, &abort_msg);
/* Close IPC channel */
sc_ipc_close(SC_IPC_CH);
#endif /* SCI_FORCE_ABORT */
return 0;
}
#ifdef CONFIG_FSL_HSIO
#define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT))
static iomux_cfg_t board_pcie_pins[] = {
SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
};
static void imx8qm_hsio_initialize(void)
{
struct power_domain pd;
int ret;
if (!power_domain_lookup_name("hsio_sata0", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("hsio_sata0 Power up failed! (error = %d)\n", ret);
}
if (!power_domain_lookup_name("hsio_pcie0", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("hsio_pcie0 Power up failed! (error = %d)\n", ret);
}
if (!power_domain_lookup_name("hsio_pcie1", &pd)) {
ret = power_domain_on(&pd);
if (ret)
printf("hsio_pcie1 Power up failed! (error = %d)\n"