Commit 46fe9eb0 authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-net

parents 1d3bcb66 8c83c030
......@@ -380,7 +380,7 @@ int miiphy_reset(const char *devname, unsigned char addr)
*/
int miiphy_speed(const char *devname, unsigned char addr)
{
u16 bmcr, anlpar;
u16 bmcr, anlpar, adv;
#if defined(CONFIG_PHY_GIGE)
u16 btsr;
......@@ -417,7 +417,12 @@ int miiphy_speed(const char *devname, unsigned char addr)
printf("PHY AN speed");
goto miiphy_read_failed;
}
return (anlpar & LPA_100) ? _100BASET : _10BASET;
if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
puts("PHY AN adv speed");
goto miiphy_read_failed;
}
return ((anlpar & adv) & LPA_100) ? _100BASET : _10BASET;
}
/* Get speed from basic control settings. */
return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET;
......@@ -433,7 +438,7 @@ miiphy_read_failed:
*/
int miiphy_duplex(const char *devname, unsigned char addr)
{
u16 bmcr, anlpar;
u16 bmcr, anlpar, adv;
#if defined(CONFIG_PHY_GIGE)
u16 btsr;
......@@ -475,7 +480,12 @@ int miiphy_duplex(const char *devname, unsigned char addr)
puts("PHY AN duplex");
goto miiphy_read_failed;
}
return (anlpar & (LPA_10FULL | LPA_100FULL)) ?
if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
puts("PHY AN adv duplex");
goto miiphy_read_failed;
}
return ((anlpar & adv) & (LPA_10FULL | LPA_100FULL)) ?
FULL : HALF;
}
/* Get speed from basic control settings. */
......
......@@ -108,26 +108,6 @@ static u_int8_t num_phy;
phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
static inline void davinci_flush_rx_descs(void)
{
/* flush the whole RX descs area */
flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
}
static inline void davinci_invalidate_rx_descs(void)
{
/* invalidate the whole RX descs area */
invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
}
static inline void davinci_flush_desc(emac_desc *desc)
{
flush_dcache_range((unsigned long)desc,
(unsigned long)desc + sizeof(*desc));
}
static int davinci_eth_set_mac_addr(struct eth_device *dev)
{
unsigned long mac_hi;
......@@ -243,10 +223,10 @@ int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
if (tmp & MDIO_USERACCESS0_ACK) {
*data = tmp & 0xffff;
return 0;
return 1;
}
return -EIO;
return 0;
}
/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
......@@ -267,7 +247,7 @@ int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
;
return 0;
return 1;
}
/* PHY functions for a generic PHY */
......@@ -394,15 +374,14 @@ static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad,
{
unsigned short value = 0;
int retval = davinci_eth_phy_read(addr, reg, &value);
if (retval < 0)
return retval;
return value;
return retval ? value : -EIO;
}
static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad,
int reg, u16 value)
{
return davinci_eth_phy_write(addr, reg, value);
return davinci_eth_phy_write(addr, reg, value) ? 0 : 1;
}
#endif
......@@ -496,8 +475,6 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
emac_rx_active_tail = rx_desc;
emac_rx_queue_active = 1;
davinci_flush_rx_descs();
/* Enable TX/RX */
writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
writel(0, &adap_emac->RXBUFFEROFFSET);
......@@ -659,8 +636,7 @@ static int davinci_eth_send_packet (struct eth_device *dev,
EMAC_CPPI_EOP_BIT);
flush_dcache_range((unsigned long)packet,
(unsigned long)packet + length);
davinci_flush_desc(emac_tx_desc);
(unsigned long)packet + ALIGN(length, PKTALIGN));
/* Send the packet */
writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
......@@ -694,8 +670,6 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)
volatile emac_desc *tail_desc;
int status, ret = -1;
davinci_invalidate_rx_descs();
rx_curr_desc = emac_rx_active_head;
if (!rx_curr_desc)
return 0;
......@@ -706,12 +680,12 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)
printf ("WARN: emac_rcv_pkt: Error in packet\n");
} else {
unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
unsigned short len =
rx_curr_desc->buff_off_len & 0xffff;
invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE);
net_process_received_packet(
rx_curr_desc->buffer,
rx_curr_desc->buff_off_len & 0xffff);
ret = rx_curr_desc->buff_off_len & 0xffff;
invalidate_dcache_range(tmp, tmp + ALIGN(len, PKTALIGN));
net_process_received_packet(rx_curr_desc->buffer, len);
ret = len;
}
/* Ack received packet descriptor */
......@@ -734,7 +708,6 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)
rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
rx_curr_desc->next = 0;
davinci_flush_desc(rx_curr_desc);
if (emac_rx_active_head == 0) {
printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
......@@ -752,13 +725,11 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)
tail_desc->next = BD_TO_HW((ulong) curr_desc);
status = tail_desc->pkt_flag_len;
if (status & EMAC_CPPI_EOQ_BIT) {
davinci_flush_desc(tail_desc);
writel(BD_TO_HW((ulong)curr_desc),
&adap_emac->RX0HDP);
status &= ~EMAC_CPPI_EOQ_BIT;
tail_desc->pkt_flag_len = status;
}
davinci_flush_desc(tail_desc);
}
return (ret);
}
......
......@@ -336,9 +336,6 @@ static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
static void fm_init_qmi(struct fm_qmi_common *qmi)
{
/* disable enqueue and dequeue of QMI */
clrbits_be32(&qmi->fmqm_gc, FMQM_GC_ENQ_EN | FMQM_GC_DEQ_EN);
/* disable all error interrupts */
out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
/* clear all error events */
......
......@@ -834,15 +834,7 @@ int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport, int sport,
#ifndef CONFIG_NET_MAXDEFRAG
#define CONFIG_NET_MAXDEFRAG 16384
#endif
/*
* MAXDEFRAG, above, is chosen in the config file and is real data
* so we need to add the NFS overhead, which is more than TFTP.
* To use sizeof in the internal unnamed structures, we need a real
* instance (can't do "sizeof(struct rpc_t.u.reply))", unfortunately).
* The compiler doesn't complain nor allocates the actual structure
*/
static struct rpc_t rpc_specimen;
#define IP_PKTSIZE (CONFIG_NET_MAXDEFRAG + sizeof(rpc_specimen.u.reply))
#define IP_PKTSIZE (CONFIG_NET_MAXDEFRAG)
#define IP_MAXUDP (IP_PKTSIZE - IP_HDR_SIZE)
......
This diff is collapsed.
......@@ -25,7 +25,10 @@
#define NFS_READLINK 5
#define NFS_READ 6
#define NFS3PROC_LOOKUP 3
#define NFS_FHSIZE 32
#define NFS3_FHSIZE 64
#define NFSERR_PERM 1
#define NFSERR_NOENT 2
......@@ -44,7 +47,15 @@
#define NFS_READ_SIZE 1024 /* biggest power of two that fits Ether frame */
#endif
#define NFS_MAXLINKDEPTH 16
/* Values for Accept State flag on RPC answers (See: rfc1831) */
enum rpc_accept_stat {
NFS_RPC_SUCCESS = 0, /* RPC executed successfully */
NFS_RPC_PROG_UNAVAIL = 1, /* remote hasn't exported program */
NFS_RPC_PROG_MISMATCH = 2, /* remote can't support version # */
NFS_RPC_PROC_UNAVAIL = 3, /* program can't support procedure */
NFS_RPC_GARBAGE_ARGS = 4, /* procedure can't decode params */
NFS_RPC_SYSTEM_ERR = 5 /* errors like memory allocation failure */
};
struct rpc_t {
union {
......@@ -65,7 +76,7 @@ struct rpc_t {
uint32_t verifier;
uint32_t v2;
uint32_t astatus;
uint32_t data[19];
uint32_t data[NFS_READ_SIZE / sizeof(uint32_t)];
} reply;
} u;
};
......
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